Altera IP Compiler for PCI Express - Manual (Page 65)

Chapter 4: IP Core Architecture 4–7
Application Interfaces
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
1 The value of the non-posted tx_cred represents that there are at least that number of
credits available. The non-posted credits displayed may be less than what is actually
available to the IP core.
LMI Interface (Hard IP Only)
The LMI bus provides access to the PCI Express configuration space in the transaction
layer. For more LMI details, refer to the
“LMI Signals—Hard IP Implementation” on
page 5–37 .
PCI Express Reconfiguration Block Interface (Hard IP Only)
The PCI Express reconfiguration bus allows you to dynamically change the read-only
values stored in the configuration registers. For detailed information refer to the
“IP
Core Reconfiguration Block Signals—Hard IP Implementation” on page 5–38 .
MSI (Message Signal Interrupt) Datapath
The MSI datapath contains the MSI boundary registers for incremental compilation.
The interface uses the transaction layer's request–acknowledge handshaking protocol.
You use the TX FIFO empty flag from the TX datapath FIFO for TX/MSI
synchronization. When the TX block application drives a packet to the Avalon-ST
adapter, the packet remains in the TX datapath FIFO as long as the IP core throttles
this interface. When you must send an MSI request after a specific TX packet, you can
use the TX FIFO empty flag to determine when the IP core receives the TX packet.
For example, you may want to send an MSI request only after all TX packets are
issued to the transaction layer. Alternatively, if you cannot interrupt traffic flow to
synchronize the MSI, you can use a counter to count 16 writes (the depth of the FIFO)
after a TX packet has been written to the FIFO (or until the FIFO becomes empty) to
ensure that the transaction layer interface receives the packet, before you issue the
MSI request.