Altera IP Compiler for PCI Express - Manual (Page 219)

Chapter 13: Reconfiguration and Offset Cancellation 13–9
Transceiver Offset Cancellation
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Transceiver Offset Cancellation
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. When you
implement the IP Compiler for PCI Express in an Arria II GX, Arria II GZ,
HardCopy IV GX, Cyclone IV GX, or Stratix IV GX device using the internal PHY, you
must compensate for this variation by including the ALTGX_RECONFIG
megafunction in your design. When you generate your ALTGX_RECONFIG module
the Offset cancellation for receiver channels option is On by default. This feature is
all that is required to ensure that the transceivers operate within the required ranges,
but you can choose to enable other features such as the Analog controls option if your
system requires this. You must connect the reconfig_fromgxb and reconfig_togxb
busses and the necessary clocks between the ALTGX instance and the
ALTGX_RECONFIG instance, as
Figure 13–1 illustrates.
The offset cancellation circuitry requires the following two clocks.
■ fixedclk_serdes —This is a free running clock whose frequency must be 125
MHz. It cannot be generated from refclk.
■ reconfig_clk — The correct frequency for this clock is device dependent
f
Refer to the appropriate device handbook to determine the frequency range for your
device as follows:
Transceiver Architecture in Volume II of the Arria II Device Handbook,
Transceivers in Volume 2 of the Cyclone IV Device Handbook, or Transceiver Architecture
in Volume 2 of the Stratix IV Device Handbook.
1 The <variant>_plus IP Compiler for PCI Express endpoint hard IP implementation
automatically includes the circuitry for offset cancellation; you do not have to add this
circuitry manually.