Altera IP Compiler for PCI Express - Manual (Page 42)

3–6 Chapter 3: Parameter Settings
Parameters in the Qsys Design Flow
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Avalon-MM Settings
The Avalon-MM Settings section of the Qsys design flow IP Compiler for PCI
Express parameter editor contains configuration settings for the PCI Express
Avalon-MM bridge.
Table 3–7 describes these parameters.
Table 3–7. Avalon-MM Configuration Settings
Parameter Value Description
Peripheral Mode
Requester/Completer,
Completer-Only,
Completer-Only
single dword
Specifies whether the IP Compiler for PCI Express component is
capable of sending requests to the upstream PCI Express devices, and
whether the incoming requests are pipelined.
Requester/Completer—Enables the IP Compiler for PCI Express to
send request packets on the PCI Express TX link as well as receiving
request packets on the PCI Express RX link.
Completer-Only—In this mode, the IP Compiler for PCI Express
can receive requests, but cannot initiate upstream requests.
However, it can transmit completion packets on the PCI Express TX
link. This mode removes the Avalon-MM TX slave port and thereby
reduces logic utilization.
Completer-Only single dword—Non-pipelined version of
Completer-Only mode. At any time, only a single request can be
outstanding. Completer-Only single dword uses fewer resources
than Completer-Only.
Control Register Access
(CRA) Avalon slave port
(Qsys flow)
Off/On
Allows read/write access to bridge registers from the Avalon
interconnect fabric using a specialized slave port. Disabling this option
disallows read/write access to bridge registers, except in the
Completer-Only single dword variations.
Auto Enable PCIe
Interrupt (enabled at
power-on)
Off/On
Turning this option on enables the IP Compiler for PCI Express
interrupt register at power-up. Turning it off disables the interrupt
register at power-up. The setting does not affect run-time
configurability of the interrupt enable register.