Altera IP Compiler for PCI Express - Manual (Page 352)

B–34 Chapter :
Recommended Incremental Compilation Flow
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
1 Altera recommends disabling the OpenCore Plus feature when compiling with this
flow. (On the Assignments menu, click Settings. Under Compilation Process
Settings
, click More Settings. Under Disable OpenCore Plus hardware evaluation
select On.)
1. Open a Quartus II project.
2. To run initial logic synthesis on your top-level design, on the Processing menu,
point to Start, and then click Start Analysis & Synthesis. The design hierarchy
appears in the Project Navigator.
3. Perform one of the following steps:
a. For Avalon-ST designs, in the Project Navigator, expand the
<variation_name>_icm module as follows: <variation_name>_example_top ->
<variation_name>_example_pipen1b:core ->. Right-click
<variation_name>:epmap and click Set as Design Partition.
b. For descriptor/data interface designs, in the Project Navigator, expand the
<variation_name>_icm module as follows: <variation_name>_example_top ->
<variation_name>_example_pipen1b:core ->
<variation_name>_icm:icm_epmap. Right-click <variation_name>_icm and click
Set as Design Partition
.
4. On the Assignments menu, click Design Partitions Window. The design partition,
Partition_<variation_name>_ or Partition_<variation_name>_icm for
descriptor/data designs, appears. Under Netlist Type, right-click and click
Post-Synthesis
.
5. To turn on incremental compilation, follow these steps:
a. On the Assignments menu, click Settings.
b. In the Category list, expand Compilation Process Settings.
c. Click Incremental Compilation.
d. Under Incremental Compilation, select Full incremental compilation.
6. To run a full compilation, on the Processing menu, click Start Compilation. Run
Design Space Explorer (DSE) if required to achieve timing requirements. (On the
Tools menu, click Launch Design Space Explorer.)
7. After timing is met, you can preserve the timing of the partition in subsequent
compilations by using the following procedure:
a. On the Assignments menu, click Design Partition Window.
b. Under the Netlist Type for the Top design partition, double-click to select
Post-Fit .
c. Right-click Partition Name column to bring up additional design partition
options and select Fitter Preservation Level.
d. Under Fitter Preservation level and double-click to select Placement And
Routing .
1 Information for the partition netlist is saved in the db folder. Do not delete this folder.