Altera IP Compiler for PCI Express - Manual (Page 74)

4–16 Chapter 4: IP Core Architecture
Physical Layer
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
The PHYMAC block is divided in four main sub-blocks:
■ MAC Lane—Both the receive and the transmit path use this block.
■ On the receive side, the block decodes the physical layer packet (PLP) and
reports to the LTSSM the type of TS1/TS2 received and the number of TS1s
received since the LTSSM entered the current state. The LTSSM also reports the
reception of FTS, SKIP and IDL ordered sets and the reception of eight
consecutive D0.0 symbols.
■ On the transmit side, the block multiplexes data from the data link layer and
the LTSTX sub-block. It also adds lane specific information, including the lane
number and the force PAD value when the LTSSM disables the lane during
initialization.
■ LTSSM—This block implements the LTSSM and logic that tracks what is received
and transmitted on each lane.
■ For transmission, it interacts with each MAC lane sub-block and with the
LTSTX sub-block by asserting both global and per-lane control bits to generate
specific physical layer packets.
■ On the receive path, it receives the PLPs reported by each MAC lane sub-block.
It also enables the multilane deskew block and the delay required before the TX
alignment sub-block can move to the recovery or low power state. A higher
layer can direct this block to move to the recovery, disable, hot reset or low
power states through a simple request/acknowledge protocol. This block
reports the physical layer status to higher layers.
■ LTSTX (Ordered Set and SKP Generation)—This sub-block generates the physical
layer packet (PLP). It receives control signals from the LTSSM block and generates
PLP for each lane of the core. It generates the same PLP for all lanes and PAD
symbols for the link or lane number in the corresponding TS1/TS2 fields.
The block also handles the receiver detection operation to the PCS sub-layer by
asserting predefined PIPE signals and waiting for the result. It also generates a
SKIP ordered set at every predefined timeslot and interacts with the TX alignment
block to prevent the insertion of a SKIP ordered set in the middle of packet.
■ Deskew—This sub-block performs the multilane deskew function and the RX
alignment between the number of initialized lanes and the 64-bit data path.
The multilane deskew implements an eight-word FIFO for each lane to store
symbols. Each symbol includes eight data bits and one control bit. The FTS, COM,
and SKP symbols are discarded by the FIFO; the PAD and IDL are replaced by
D0.0 data. When all eight FIFOs contain data, a read can occur.
When the multilane lane deskew block is first enabled, each FIFO begins writing
after the first COM is detected. If all lanes have not detected a COM symbol after 7
clock cycles, they are reset and the resynchronization process restarts, or else the
RX alignment function recreates a 64-bit data word which is sent to the data link
layer.