Altera IP Compiler for PCI Express - Manual (Page 147)

Chapter 5: IP Core Interfaces 5–61
Test Signals
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Test Interface Signals—Soft IP Implementation
Table 5–34 describes the test signals for the soft IP implementation.
Table 5–34. Test Interface Signals—Soft IP Implementation
Signal I/O Description
test_in[31:0] I
The test_in bus provides runtime control for specific IP core
features. For normal operation, this bus can be driven to all 0's. The
following bits are defined:
[0]—Simulation mode. This signal can be set to 1 to accelerate
MegaCore function initialization by changing many initialization
count.
[2:1]—reserved.
[3]–FPGA mode. Set this signal to 1 for an FPGA implementation.
[4]—reserved.
[6:5] Compliance test mode. Disable/force compliance mode:
■ bit 0—completely disables compliance mode; never enter
compliance mode.
■ bit 1—forces compliance mode. Forces entry to compliance mode
when timeout is reached in polling.active state (and not all lanes
have detected their exit condition).
[7]–Disables low power state negotiation. When asserted, this signal
disables all low power state negotiation. This bit is set to 1 for Qsys.
[11:8]—You must tie these signals low.
[15:13]—selects the lane.
[32:16, 12]—reserved.
test_out[511:0] or [8:0] for ×1 or ×4
test_out[127:0] or [8:0] for ×8
O
The test_out bus allows you to monitor the PIPE interface When you
choose the 9-bit test_out bus width, a subset of the test_out
signals are brought out as follows:
■ bits[4:0] = test_out[4:0] on the ×8 IP core.
bits[4:0] = test_out[324:320] on the ×4/×1 IP core.
■ bits[8:5] = test_out[91:88] on the ×8 IP core.
bits[8:5] = test_out[411:408] on the ×4/×1 IP core.
The following bits are defined when you choose the larger bus:
■ [7:0]—txdata.
■ [8]—txdatak.
■ [9]—txdetectrx.
■ [10]—txelecidle.
■ [11]—txcompl.
■ [12]—rxpolarity.
■ [14:13]—powerdown.
■ [22:15]—rxdata.
■ [23]—rxdatak.
■ [24]—rxvalid.
■ [63:25]—reserved.