Altera IP Compiler for PCI Express - Manual (Page 358)

C–4 Chapter :
Descriptor/Data Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Table C–6 shows the typical expected performance and resource utilization of
Stratix IV (EP4SGX230KF40C2) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 11.0.
Descriptor/Data Interface
This section tabulates the typical expected performance and resource utilization of the
listed device families for various parameters when using the descriptor/data
interface, with the OpenCore Plus evaluation feature disabled and the following
parameter settings:
■ On the Buffer Setup page, for ×1, ×4, and ×8 configurations:
■ Maximum payload size set to 256 Bytes unless specified otherwise.
■ Desired performance for received requests and Desired performance for
completions both set to Medium unless specified otherwise.
■ On the Capabilities page, the number of Tags supported set to 16 for all
configurations unless specified otherwise.
Size and performance tables appear here for the following device families:
■ Arria GX Devices
■ Cyclone III Family
■ Stratix II GX Devices
■ Stratix III Family
■ Stratix IV Family
Arria GX Devices
Table C–7 shows the typical expected performance and resource utilization of
Arria GX (EP1AGX60DF780C6) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 11.0.
Table C–6. Performance and Resource Utilization, Avalon-MM Interface - Stratix IV Family
Parameters Size
×1/ ×4
Internal
Clock (MHz)
Combinational
ALUTs
Dedicated
Registers
M9K Memory
Blocks
×1 125 6800 4700 25
×4 125 8300 5600 25
Table C–7. Performance and Resource Utilization, Descriptor/Data Interface - Arria GX Devices
Parameters Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channels
Combinational
ALUTs
Logic
Registers
Memory Blocks
M512 M4K
×1 125 1 5200 3600 1 21
×1 125 2 6400 4400 2 13