Altera IP Compiler for PCI Express - Manual (Page 209)

Chapter 12: Error Handling 12–7
Uncorrectable and Correctable Error Status Bits
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Figure 12–2 illustrates the Correctable Error Status register. The default value of all the
bits of this register is 0. An error status bit that is set indicates that the error condition
it represents has been detected. Software may clear the error status by writing a 1 to
the appropriate bit.
Figure 12–2. Correctable Error Status Register
Rsvd Rsvd Rsvd
Header Log Overflow Status
Corrected Internal Error Status
Advisory Non-Fatal Error Status
Replay Timer Timeout Status
REPLAY_NUM Rollover Status
Bad DLLP Status
Bad TLP Status
Receiver Error Status
16 15 14 13 12 11 9 8 7 6 5 1 0 31