Altera IP Compiler for PCI Express - Manual (Page 162)

6–14 Chapter 6: Register Descriptions
Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
0x010 Base Address 0 Base Address Registers (Offset 10h/14h)
0x014 Base Address 1 Base Address Registers (Offset 10h/14h)
0x018
Secondary Latency Timer Subordinate Bus
Number Secondary Bus Number Primary Bus
Number Secondary Latency Timer (Offset 1Bh)/Type 1
Configuration Space Header/ /Primary Bus Number
(Offset 18h)
0x01C Secondary Status I/O Limit I/O Base
Secondary Status Register (Offset 1Eh) / Type 1
Configuration Space Header
0x020 Memory Limit Memory Base Type 1 Configuration Space Header
0x024
Prefetchable Memory Limit Prefetchable Memory
Base
Prefetchable Memory Base/Limit (Offset 24h)
0x028 Prefetchable Base Upper 32 Bits Type 1 Configuration Space Header
0x02C Prefetchable Limit Upper 32 Bits Type 1 Configuration Space Header
0x030 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits Type 1 Configuration Space Header
0x034 Reserved Capabilities PTR Type 1 Configuration Space Header
0x038 Expansion ROM Base Address Type 1 Configuration Space Header
0x03C Bridge Control Interrupt Pin Interrupt Line Bridge Control Register (Offset 3Eh)
Table 6-4. MSI Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
0x050 Message Control Next Cap Ptr Capability ID MSI and MSI-X Capability Structures
0x054 Message Address MSI and MSI-X Capability Structures
0x058 Message Upper Address MSI and MSI-X Capability Structures
0x05C Reserved Message Data MSI and MSI-X Capability Structures
Table 6-5. MSI-X Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
0x68 Message Control Next Cap Ptr Capability ID MSI and MSI-X Capability Structures
0x6C MSI-X Table Offset BIR MSI and MSI-X Capability Structures
0x70 Pending Bit Array (PBA) Offset BIR MSI and MSI-X Capability Structures
Table 6-6. Power Management Capability Structure, Rev2 Spec: Power Management Capability Structure
0x078 Capabilities Register Next Cap PTR Cap ID PCI Power Management Capability Structure
0x07C
Data PM Control/Status Bridge Extensions Power
Management Status & Control
PCI Power Management Capability Structure
Table 6-7. PCI Express Capability Structure Version 1.0a and 1.1 (Note 1), Rev2 Spec: PCI Express Capabilities Register
and PCI Express Capability List Register
0x080
PCI Express Capabilities Register Next Cap PTR
Capability ID PCI Express Capabilities Register / PCI Express
Capability List Register
0x084 Device capabilities Device Capabilities Register
0x088 Device Status Device Control Device Status Register/Device Control Register
0x08C Link capabilities Link Capabilities Register
0x090 Link Status Link Control Link Status Register/Link Control Register
0x094 Slot capabilities Slot Capabilities Register
0x098 Slot Status Slot Control Slot Status Register/ Slot Control Register
0x09C Reserved Root Control Root Control Register
Table 6–23. Correspondence Configuration Space Registers and PCIe Base Specification Rev. 2.0 Description (Part 3
of 5)
Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 Corresponding Section in PCIe Specification