Altera IP Compiler for PCI Express - Manual (Page 126)

5–40 Chapter 5: IP Core Interfaces
Avalon-ST Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Table 5–20 outlines the use of the various fields of the Power Management
Capabilities register.
pm_event I
Power Management Event. This signal is only available in the hard IP Endpoint
implementation.
Endpoint—initiates a a power_management_event message (PM_PME) that is sent to the
root port. If the IP core is in a low power state, the link exists from the low-power state to
send the message. This signal is positive edge-sensitive.
pm_data[9:0] I
Power Management Data. This signal is only available in the hard IP implementation.
This bus indicates power consumption of the component. This bus can only be
implemented if all three bits of AUX_power (part of the Power Management Capabilities
structure) are set to 0. This bus includes the following bits:
■ pm_data[9:2] : Data Register: This register is used to maintain a value associated with
the power consumed by the component. (Refer to the example below)
■ pm_data[1:0] : Data Scale: This register is used to maintain the scale used to find the
power consumed by a particular component and can include the following values:
b’00: unknown
b’01: 0.1 ×
b’10: 0.01 ×
b’11: 0.001 ×
For example, the two registers might have the following values:
■ pm_data[9:2]: b’1110010 = 114
■ pm_data[1:0]: b’10, which encodes a factor of 0.01
To find the maximum power consumed by this component, multiply the data value by the
data Scale (114 × .01 = 1.14). 1.14 watts is the maximum power allocated to this
component in the power state selected by the data_select field.
pm_auxpwr I
Power Management Auxiliary Power: This signal is only available in the hard IP
implementation. This signal can be tied to 0 because the L2 power state is not supported.
Table 5–19. Power Management Signals
Signal I/O Description
Table 5–20. Power Management Capabilities Register Field Descriptions (Part 1 of 2)
Bits Field Description
[31:24] Data register This field indicates in which power states a function can assert the PME# message.
[22:16] reserved —
[15] PME_status
When this signal is set to 1, it indicates that the function would normally assert the PME#
message independently of the state of the PME_en bit.
[14:13] data_scale
This field indicates the scaling factor when interpreting the value retrieved from the data
register. This field is read-only.
[12:9] data_select
This field indicates which data should be reported through the data register and the
data_scale
field.
[8] PME_EN
1: indicates that the function can assert PME#
0: indicates that the function cannot assert PME#