Altera IP Compiler for PCI Express User Manual

Page 316

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background image

A–4

Chapter :

TLP Packet Format with Data Payload

IP Compiler for PCI Express User Guide

August 2014

Altera Corporation

Byte 0

0 1 1 0 0 0 0 0 0

TC

0 0 0 0 TD

EP

Att

r

0 0

Length

Byte 4

Requestor ID

Tag

Last BE

First BE

Byte 8

Address[63:32]

Byte 12

Address[31:2]

0 0

Table A–12. Memory Write Request, 64-Bit Addressing

Table A–13. Configuration Write Request Root Port (Type 1)

+0

+1

+2

+3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

6

5 4 3 2 1 0 7 6 5 4 3 2 1 0

Byte 0

0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD

EP

0 0 0 0 0 0 0 0 0 0 0 0 0 1

Byte 4

Requestor ID

Tag

0 0 0 0 First BE

Byte 8

Bus Number

Device No

0

0

0 0

Ext Reg

Register No

0 0

Byte 12

Reserved

Table A–14. I/O Write Request

+0

+1

+2

+3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

6

5 4 3 2 1 0 7 6 5 4 3 2 1 0

Byte 0

0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TD

EP

0 0 0 0 0 0 0 0 0 0 0 0 0 1

Byte 4

Requestor ID

Tag

0 0 0 0 First BE

Byte 8

Address[31:2]

0 0

Byte 12

Reserved

Table A–15. Completion with Data

+0

+1

+2

+3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

6

5 4

3 2 1 0

7 6 5 4 3 2 1 0

Byte 0

0 1 0 0 1 0 1 0 0

TC

0 0 0 0 TD

EP

Att

r

0 0

Length

Byte 4

Completer ID

Status

B

Byte Count

Byte 8

Requestor ID

Tag

0

Lower Address

Byte 12

Reserved

Table A–16. Completion Locked with Data

+0

+1

+2

+3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

6

5 4

3 2 1 0

7 6 5 4 3 2 1 0

Byte 0

0 1 0 0 1 0 1 1 0

TC

0 0 0 0 TD

EP

Att

r

0 0

Length

Byte 4

Completer ID

Status

B

Byte Count

Byte 8

Requestor ID

Tag

0

Lower Address

Byte 12

Reserved

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