Altera IP Compiler for PCI Express - Manual (Page 344)

B–26 Chapter :
Incremental Compile Module for Descriptor/Data Examples
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Incremental Compile Module for Descriptor/Data Examples
When the descriptor/data IP Compiler for PCI Express is generated, the example
designs are generated with an Incremental Compile Module. This module facilitates
timing closure using Quartus II incremental compilation and is provided for
backward compatibility only. The ICM facilitates incremental compilation by
providing a fully registered interface between the user application and the PCI
Express transaction layer. (Refer to
Figure B–23 ) With the ICM, you can lock down the
placement and routing of the IP Compiler for PCI Express to preserve timing while
changes are made to your application. Altera provides the ICM as clear text to allow
its customization if required.
ko_cpl_spc_vc <n>[19:0]
(1)
O
This static signal reflects the amount of RX buffer space reserved for completion
headers and data. It provides the same information as is shown in the RX buffer
space allocation table of the parameter editor Buffer Setup page (refer to
“Buffer
Setup” on page 3–16 ). The bit field assignments for this signal are:
■ ko_cpl_spc_vc<n>[7:0] : Number of completion headers that can be stored
in the RX buffer.
■ ko_cpl_spc_vc<n>[19:8] : Number of 16-byte completion data segments
that can be stored in the RX buffer.
The application layer logic is responsible for making sure that the completion
buffer space does not overflow. It needs to limit the number and size of
non-posted requests outstanding to ensure this.
(2)
Notes to Table B–11 :
(1) where <n> is 0 - 3 for the ×1 and ×4 cores, and 0 - 1 for the ×8 core
(2) Receive Buffer size consideration: The receive buffer size is variable for the IP Compiler for PCI Express soft IP variations and fixed to 16 KByte
per VC for the hard IP variations.The RX Buffer size is set to accommodate optimum throughput of the PCIe link.The receive buffer collects all
incoming TLPs from the PCIe link which consists of posted or non-posted TLPs. When configured as an endpoint, the IP Compiler for PCI
Express credit advertising mechanism prevents the RX Buffer from overflowing for all TLP packets except incoming completion TLP packets
because the endpoint variation advertises infinite credits for completion, per the
PCI Express Base Specification Revision 1.1 or 2.0 .
Therefore for endpoint variations, there could be some rare TLP completion sequences which could lead to a RX Buffer overflow. For example,
a sequence of 3 dword completion TLP using a qword aligned address would require 6 dwords of elapsed time to be written in the RX buffer:
3 dwords for the TLP header, 1 dword for the TLP data, plus 2 dwords of PHY MAC and data link layer overhead. When using the Avalon-ST
128-bit interface, reading this TLP from the RX Buffer requires 8 dwords of elapsed time.Therefore, theoretically, if such completion TLPs are
sent back-to-back, without any gap introduced by DLLP, update FC or a skip character, the RX Buffer will overflow because the read frequency
does not offset the write frequency. This is certainly an extreme case and in practicalities such a sequence has a very low probably of occurring.
However, to ensure that the RX buffer never overflows with completion TLPs, Altera recommends building a circuit in the application layer that
arbitrates the upstream memory read request TLP based on the available space in the completion buffer.
Table B–11. Completion Interface Signals
Signal I/O Description