Rockwell Automation 1761-HHP-B30 MicroLogix 1000 with Hand-Held Programmer (HHP) - Manual (Page 252)

Chapter 14
Using High-Speed Counter Instructions
14–2
Use the high-speed counter instructions to perform specific actions after a
preset count is reached. These actions include the automatic and immediate
execution of the high-speed counter interrupt routine (file 4) and the
immediate update of outputs based on a source and mask pattern you set.
Counter Data File Elements
The high-speed counter instructions reference counter C0. The HSC
instruction is fixed at C0. It is comprised of three words. Word 0 is the
status word, containing 15 status bits. Word 1 is the preset value. Word 2 is
the accumulated value. Once assigned to the HSC instruction, C0 is not
available as an address for any other counter instructions.
CU CD DN OV UN UA HP LP IV IN IH IL PE LS IE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Preset Value
Accumulator Value
CU = Counter Up Enable Bit
CD = Counter Down Enable Bit
DN = High Preset Reached Bit
OV = Overflow Occurred Bit
UN = Underflow Occurred Bit
UA = Update High-Speed Counter Accumulator Bit
HP = Accumulator
≥
High Preset Bit
LP = Accumulator
≤
Low Preset Bit
IV = Overflow Caused High-Speed Counter Interrupt Bit
IN = Underflow Caused High-Speed Counter Interrupt Bit
IH = High Preset Reached Caused Interrupt Bit
IL = Low Preset Reached Caused Interrupt Bit
PE = High-Speed Counter Interrupt Pending Bit
LS = High-Speed Counter Interrupt Lost Bit
IE = High-Speed Counter Interrupt Enable Bit
Word 0
Word 1
Word 2
Word
Status
Counter preset and accumulated values are stored as signed integers.
Using Status Bits
The high-speed counter status bits are retentive. When the high-speed
counter is first configured, bits 3–7, 14, and 15 are reset and bit 1 (IE) is set.
•
Counter Up Enable Bit CU (bit 15) is used with all of the high-speed
counter types. If the HSC instruction is true, the CU bit is set to one. If
the HSC instruction is false, the CU bit is set to zero. Do not write to this
bit.
•
Counter Down Enable Bit CD (bit 14) is used with the Bidirectional
Counters (modes 3–8). If the HSC instruction is true, the CD bit is set to
one. If the HSC instruction is false, the CD bit is set to zero. Do not
write to this bit.
•
High Preset Reached Bit DN (bit 13) For the Up Counters (modes 1
and 2), this bit is an edge triggered latch bit. This bit is set when the high
preset is reached. You can reset this bit with an OTU instruction or by
executing an RAC or RES instruction.
The DN bit is a reserved bit for all other Counter options (modes 3–8).
High-Speed Counter
Instructions Overview