Rockwell Automation 1761-HHP-B30 MicroLogix 1000 with Hand-Held Programmer (HHP) - Manual (Page 272)

Chapter 14
Using High-Speed Counter Instructions
14–22
Operation
When the high-speed counter interrupt is enabled, user subroutine (file 4) is
executed when:
•
A high or low preset is reached.
•
An overflow or underflow occurs.
When in RSSN mode and in an idle condition, the high-speed counter
interrupt is held off until the next scan trigger is received from the
programming device. The high-speed counter accumulator counts while idle.
If the HSE is subsequently executed after the pending bit is set, the interrupt
is executed immediately.
The default state of the high-speed counter interrupt is enabled (the IE bit is
set to 1).
If the high-speed counter interrupt routine is executing and another
high-speed counter interrupt occurs, the second high-speed counter interrupt
is saved but is considered pending. (The PE bit is set.) The second interrupt
is executed immediately after the first one is finished executing. If a
high-speed counter interrupt occurs while a high-speed counter interrupt is
pending, the most recent high-speed counter interrupt is lost and the LS bit is
set.
Using HSD
Entering the Instruction
You enter the instruction from within the program monitor functional area.
P 0 0 8 H S D C N T R
C 0 0
Operation
The HSD instruction disables the high-speed counter interrupt, preventing
the interrupt subroutine from being executed.
If the HSE is subsequently executed after the pending bit is set, the interrupt
is executed immediately.
This HSD instruction does not cancel an interrupt, but results in the pending
bit (C0/PE) being set when:
•
A high or low preset is reached.
•
An overflow or underflow occurs.
ENT
4
To enter the function code, press:
7 1
FUN