Rockwell Automation 1761-HHP-B30 MicroLogix 1000 with Hand-Held Programmer (HHP) - Manual (Page 400)

Appendix B
Programming Reference
B–5
Address Bit Classification Description1
S1/13 Major Error
Halted Dynamic
Configuration When you clear bit S:1/13 using a programming device, the
controller mode changes from fault to Remote Program. You
can move a value to S:6, then set S:1/13 in your ladder program
to generate an application specific major error. All application
generated faults are recoverable regardless of the value used.
Note: Once a major fault state exists, you must correct the
condition causing the fault, and you must also clear this bit in
order for the controller to accept a mode change attempt (into
REM Run or REM Test). Also, clear S:6 to avoid the confusion
of having an error code but no fault condition.
S1/13 Major Error
Halted Dynamic
Configuration Note: Do not re-use error codes that are defined later in this
appendix as application specific error codes. Instead, create your
own unique codes. This prevents you from confusing application
errors with system errors. We recommend using error codes
FFOO to FFOF to indicate application specific major errors.
S1/14 OEM Lock Static Configuration Using this bit you can control access to a controller file. 1 1 M L c a ic fi ra i
To program this feature, select “Future Access Disallow” when
saving your program.
When this bit is cleared, it indicates that any compatible
programming device can access the ladder program (provided
that password conditions are satisfied).
S1/15 First Pass Status Use this bit to initialize your program as the application requires.
When this bit is set by the controller, it indicates that the first
scan of the user program is in progress (following power up in
the RUN mode or entry into a REM Run or REM Test mode).
The controller clears this bit following the first scan.
This bit is set during execution of the startup protection fault
routine. Refer to S:1/9 for more information.
S2/0 STI Pending Status When set, this bit indicates that the STI timer has timed out and
the STI routine is waiting to be executed. This bit is cleared
upon starting the STI routine, ladder program, exit of the REM
Run or Test mode, or execution of a true STS instruction.
S2/1 STI Enabled Status and Static
Configuration This bit may be set or reset using the STS, STE, or STD
instruction. If set, it allows execution of the STI if the STI
setpoint S:30 is non-zero. If clear, when an interrupt occurs, the
STI subroutine does not execute and the STI Pending bit is set.
The STI Timer continues to run when this bit is disabled. The
STD instruction clears this bit.
If this bit is set or reset editing the status file online, the STI is
not affected. If this bit is set, the bit allows execution of the STI.
If this bit is reset editing the status file offline, the bit disallows
execution of the STI.
S2/2 STI Executing Status When set, this bit indicates that the STI timer has timed out and
the STI subroutine is currently being executed. This bit is
cleared upon completion of the STI routine, ladder program, or
REM Run or Test mode.
S2/3 to S2/4 Reserved NA NA
S2/5 ➀ Incoming
Command
Pending Bit Status This bit is set when the processor determines that another node
on the network has requested information or supplied a
command to it. This bit can be set at any time. This bit is cleared
when the processor services the request (or command).
➀ Valid for Series C discrete only.
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Reference