Rockwell Automation 1761-HHP-B30 MicroLogix 1000 with Hand-Held Programmer (HHP) - Manual (Page 253)

Chapter 14
Using High-Speed Counter Instructions
14–3
•
Overflow Occurred Bit OV (bit 12) For the Up Counters (modes 1 and
2), this bit is set by the controller when the high preset is reached if the
DN bit is set.
For the Bidirectional Counters (modes 3–8), the OV bit is set by the
controller after the hardware accumulator transitions from 32,767 to
–32,768. You can reset this bit with an OTU instruction or by executing
an RAC or RES instruction for both the up and bidirectional counters.
•
Underflow Occurred Bit UN (bit 11) is a reserved bit for the Up
Counters (modes 1 and 2). Do not write to this bit.
For the Bidirectional Counters (modes 3–8), the UN bit is set by the
controller when the hardware accumulator transitions from –32,768 to
+
32,767. You can reset this bit with an OTU instruction or by executing
an RAC or RES instruction.
•
Update High-Speed Counter Accumulator Bit UA (bit 10) is used
with an OTE instruction to update the instruction image accumulator
value with the hardware accumulator value. (The HSC instruction also
performs this operation each time the rung with the HSC instruction is
evaluated as true.)
•
Accumulator
≥
High Preset Bit HP (bit 9) is a reserved bit for all Up
Counters (modes 1 and 2).
For the Bidirectional Counters (modes 3–8), if the hardware accumulator
becomes greater than or equal to the high preset, the HP bit is set. If the
hardware accumulator becomes less than the high preset, the HP bit is
reset by the controller. Do not write to this bit. (Exception – you can set
or reset this bit during the initial configuration of the HSC instruction.
See page 14–23 for more information.)
•
Accumulator
≤
Low Preset Bit LP (bit 8) is a reserved bit for all Up
Counters.
For the Bidirectional Counters, if the hardware accumulator becomes less
than or equal to the low preset, the LP bit is set by the controller. If the
hardware accumulator becomes greater than the low preset, the LP bit is
reset by the controller. Do not write to this bit. (Exception – you can set
or reset this bit during the initial configuration of the HSC instruction.
See page 14–23 for more information.)
•
Overflow Caused High-Speed Counter Interrupt Bit IV (bit 7) is set
to identify an overflow as the cause for the execution of the high-speed
counter interrupt routine. The IN, IH, and IL bits are reset by the
controller when the IV bit is set. Examine this bit at the start of the
high-speed counter interrupt routine (file 4) to determine why the
interrupt occurred.
•
Underflow caused User Interrupt Bit IN (bit 6) is set to identify an
underflow as the cause for the execution of the high-speed counter
interrupt routine. The IV, IH, and IL bits are reset by the controller when
the IN bit is set. Examine this bit at the start of the high-speed counter
interrupt routine (file 4) to determine why the interrupt occurred.
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