Rockwell Automation 1761-HHP-B30 MicroLogix 1000 with Hand-Held Programmer (HHP) - Manual (Page 254)

Chapter 14
Using High-Speed Counter Instructions
14–4
•
High Preset Reached Caused User Interrupt Bit IH (bit 5) is set to
identify a high preset reached as the cause for the execution of the
high-speed counter interrupt routine. The IV, IN, and IL bits are reset by
the controller when the IH bit is set. Examine this bit at the start of the
high-speed counter interrupt routine (file 4) to determine why the
interrupt occurred.
•
Low Preset Reached Caused High-Speed Counter Interrupt Bit IL
(bit 4) is set to identify a low preset reached as the cause for the execution
of the high-speed counter interrupt routine. The IV, IN, and IH bits are
reset by the controller when the IL bit is set. Examine this bit at the start
of the high-speed counter interrupt routine (file 4) to determine why the
interrupt occurred.
•
High-Speed Counter Interrupt Pending Bit PE (bit 3) is set to
indicate that a high-speed counter interrupt is waiting for execution. This
bit is cleared by the controller when the high-speed counter interrupt
routine begins executing. This bit is reset if an RAC or RES instruction is
executed. Do not write to this bit.
•
High-Speed Counter Interrupt Lost Bit LS (bit 2) is set if an
high-speed counter interrupt occurs while the PE bit is set. You can reset
this bit with an OTU instruction or by executing an RAC or RES
instruction.
•
High-Speed Counter Interrupt Enable Bit IE (bit 1) is set when the
high-speed counter interrupt is enabled to run when an high-speed counter
interrupt condition occurs. It is reset when the interrupt is disabled. This
bit is also set when the high-speed counter is first configured. Do not
write to this bit.
Use this instruction to configure the high-speed counter. Only one HSC
instruction can be used in a program. The high-speed counter is not
operational until the first true execution of the HSC instruction. When the
HSC rung is false, the high-speed counter is disabled from counting but all
other HSC features are operational.
The Counter address of the HSC instruction is fixed at C0.
After the HSC is configured, the image accumulator is updated with the
current hardware accumulator value every time the HSC instruction is
evaluated as true or false.
Entering Parameters
Enter the following parameters when programming this instruction:
•
Type indicates the counter selected. Refer to page 14–5 for making your
high-speed counter selection. Each type is available with reset and hold
functionality.
•
High Preset is the accumulated value that triggers a user-specified action
such as updating outputs or generating an high-speed counter interrupt.
•
Accumulator is the number of accumulated counts.
Execution Times
(µ
sec
)
when:
True False
21.00 21.00
HSC
HIGH SPEED COUNTER
Type
Up (Res,Hld)
Counter C5:0
High Preset 1
Accum 1
(CD)
(CU)
(DN)
Ladder representation:
High-Speed Counter (HSC)