Rockwell Automation FlexPak 3000 Digital DC Drive Version 4.3 - Manual (Page 21)

Configuring the Speed Reference 4-1
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Configuring the Speed Reference
The FlexPak 3000 drive can be configured as a speed regulator or as an armature
voltage regulator, depending on the value of
FEEDBACK SELECT (P.200). In this chapter,
the phrase “speed loop” refers to either configuration unless otherwise noted.
The drive can also be configured as either a speed/voltage or current regulator. If the
drive is to be configured as a current regulator, skip this chapter and see Chapter 6.
The speed reference is the speed the speed loop tries to maintain. The drive
processes and scales the speed reference input for use by the speed loop.
The speed loop uses the selected reference value and attempts to keep the speed
feedback from the motor equal to the reference value. If the feedback is less than the
reference, the speed loop increases the motor speed by commanding more current to
the motor. If the reference is less than the feedback, the speed loop decreases the
motor speed by commanding less current to the motor. The speed loop tries to
minimize the amount of error between the speed reference and the speed feedback.
The speed and accuracy with which the speed loop responds to reference or motor
load changes is determined by the speed loop parameters.
Processing the speed reference consists of three major blocks, shown in figure 4.1.
In the speed reference source select block, the selected reference is scaled and the
amplitude is limited. See section 4.1.
In the speed reference ramp block, the reference value from the speed reference
source select block is modified based on your parameter settings. For example, trim
and rate limiting are applied. See section 4.3.
In the speed reference mode select block, the ramped speed reference signal is
summed with current compounding and outer control loop outputs. See section 4.3.
Figure 4.1 – Speed Reference Overview
(Figure 9.1)
(Figure 4.7)
(Figure 4.5)
(Figure 4.2)
To Figure 5.1,
Speed Loop Block
Diagram
To Figure 6.2,
Current Minor Loop
Block Diagram