Intel PXA26X - Manual (Page 103)

Intel® PXA26x Processor Family Developer’s Manual 3-37
Clocks and Power Manager
3.6.2 Clock Enable Register (CKEN)
CKEN enables or disables the clocks to most of the peripheral units (refer to Table 3-22 ). For
lowest power consumption, disable any unused unit clock by clearing the appropriate bit.
Table 3-22. CKEN Register Bitmap and Bit Definitions (Sheet 1 of 2)
0x4130 0004 Clock Enable Register (CKEN) Clocks Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Re
s
e
rv
e
d
C
KEN
1
6
Re
s
e
rv
e
d
C
KEN
1
6
C
KEN
1
3
C
KEN
1
2
CK
EN1
1
C
KEN
1
0
C
KEN
9
C
KEN
8
C
KEN
7
C
KEN
6
C
KEN
5
C
KEN
4
C
KEN
3
C
KEN
2
C
KEN
1
C
KEN
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[31:17] —
Reserved.
Read undefined and must always be written with zeroes.
16 CKEN16
LCD UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
15 —
Reserved.
Reads undefined and must always be written with a zero.
14 CKEN14
I2C UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
13 CKEN13
FICP UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
12 CKEN12
MMC UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
11 CKEN11
USB UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
This bit must be set to allow the 48Mhz clock output on GP7 alternate function 1.
10 CKEN10
AUDIO SSP UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
9 CKEN9
NETWORK SSP UNIT CLOCK ENABLE:
0 – Clock to the unit is disabled
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets