Intel PXA26X - Manual (Page 278)

7-10 Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
7.3.5.2 Active-Display Timing
In active display mode (LCCR0[PAS]=1), L_PCLK toggles continuously as long as the LCD
controller is enabled. The other pins function as:
L_BIAS – Output enable. When asserted, the LCD latches L_DD data using L_PCLK.
L_LCLK – Horizontal synchronization signal (HSYNC)
L_FCLK – Vertical synchronization signal (VSYNC)
If an output FIFO underrun occurs, the data on the L_DD pins is repeated, L_BIAS stays asserted,
and L_PCLK keeps running. As valid data enters the output FIFO, it is sent to the display.
Additional pixel clocks are inserted at the end of the line to drain the remaining valid pixels from
the output FIFO before HSYNC is asserted. This mechanism allows an underrun to corrupt only a
single line rather than an entire frame.
7.3.5.3 Pixel Data Pins (L_DDx)
Pixel data is removed from the bottom of the output FIFO and driven in parallel onto the LCD data
lines on the edge of the pixel clock selected by Pixel Clock Polarity (LCCR3[PCP]). Pixel data pins
usage:
• For a 4-bit wide bus, data goes out on the LCD data lines L_DD[3:0].
• For an 8-bit wide bus, data goes out on L_DD[7:0].
• For a 16-bit bus, data goes out on L_DD[15:0].
• In monochrome dual-panel mode, the pixels for the upper half of the screen go out on
L_DD[3:0] and those for the lower half on L_DD[7:4].
• In color dual-panel mode, the upper panel pixels go out on L_DD[7:0] and the lower panel
pixels on L_DD[15:8].
The LCD data pins are driven at their last value during the inactive portion of the LCD frame.
7.3.6 Direct Memory Access
Values for palette RAM entries and encoded pixel data are stored in off-chip memory. These values
and pixel data are transferred to the LCD controller’s input FIFO buffers, on a demand basis, using
the LCD controller’s dedicated DMA controller (DMAC). The LCD’s descriptor-based DMAC
contains two channels that transfer data from external memory to the input FIFOs. One channel is
used for single-panel displays and two are used for dual-panel displays.
The LCD controller issues a service request to the DMAC after it has been initialized and enabled.
The DMAC automatically performs eight word transfers, filling four entries of the input FIFO.
Values are fetched from the bottom of the FIFO, one entry at a time, and each 64-bit value is
unpacked into individual-pixel encodings of 1-, 2-, 4-, 8-, or 16-bits each. After the value is
removed from the bottom of the FIFO, the entry is invalidated, and all data in the FIFO is shifted
down one entry. When four of the entries are empty, a service request is issued to the DMAC. If the
DMAC is not able to keep the FIFO filled with enough pixel data (due to insufficient external
memory access speed) and the FIFO is emptied, the appropriate FIFO underrun status bit is set (bit
LCSR[IUL] or LCSR[IUU]), and an interrupt request is issued (unless it is masked).