1 expansion memory timing configuration register, Table 6-27. mcmemx register bitmap, Table 6-28. mcattx register bitmap – Intel PXA26X User Manual

Page 248

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6-58

Intel® PXA26x Processor Family Developer’s Manual

Memory Controller

6.9.1

Expansion Memory Timing Configuration Register

MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, and MCIO1 are read/write registers that
contain control bits for configuring the timing of the 16-bit PC Card/Compact Flash interface.

The programming of each of the four fields in each of the six registers lets software to individually
select the duration of accesses to I/O, common memory, and attribute space for each of two 16-bit
PC Card/Compact Flash card slots.

Refer to

Table 6-27

,

Table 6-28

, and

Table 6-29

for bitmaps of the MCMEMx registers. Also refer

to

Table 6-30

. Refer to

Figure 6-27

and

Figure 6-28

for a 16-bit PC Card/Compact Flash timing

diagram.

Table 6-27. MCMEMx Register Bitmap

0x4800 0028

0x4800 002C

MCMEM0
MCMEM1

processor

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

R

eser

ved

ME

Mx

_

HO

L

D

R

eser

ved

ME

Mx

_

AS

ST

ME

Mx

_

SE

T

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bits

Name

Description

31:20

Reserved

19:14

MCMEMx_

HOLD

Minimum Number of memory clocks to set up address before command assertion for
MCMEM for socket x is equal to MCMEMx_HOLD + 2.

13:12

Reserved

11:7

MCMEMx_

ASST

Code for the command assertion time – See

Table 6-30

for a description of this code and

its affects on the command assertion.

6:0

MCMEMx_

SET

Minimum Number of memory clocks to set up address before command assertion for
MCMEM for socket x is equal to MCMEMx_SET + 2.

Table 6-28. MCATTx Register Bitmap

0x4800 0030
0x4800 0030

MCATT0
MCATT1

Processor

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

R

eser

ved

A

TTx_

HO

L

D

R

eser

ved

A

TTx_

ASS

T

A

TTx_

SET

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bits

Name

Description

31:20

Reserved

19:14

MCATTx_

HOLD

Minimum Number of memory clocks to set up address before command assertion for
MCATT for socket x is equal to MCATTx_HOLD + 2.

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