Intel PXA26X - Manual (Page 140)

4-32 Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
4.3 Real-Time Clock (RTC)
Use the RTC to configure a clock source with a wide range of frequencies. Typically, the RTC is set
to be a 1 Hz output and is utilized as a system time keeper. There is also an alarm feature that
enables an interrupt or a wake up event when the RTC output clock increments to a pre-set value.
4.3.1 Real-Time Clock Operation
The real-time clock (RTC) provides a general-purpose real-time reference for your design. The
RTC Counter register (RCNR) is initialized to zero after a hardware reset or a watchdog reset. It is
a free running counter and starts incrementing the count value after the deassertion of reset. The
counter is incremented one 32-KHz cycle after the rising edge of the Hz clock. Since the high
phase of the 1-Hz clock is one 32-KHz cycle wide, it appears to increment on the falling edge of
the 1-Hz clock. Set this counter to the desired value. If the counter is set to a value other than zero,
write the desired value to the RCNR. The value of the counter is unaffected by transitions into and
out of sleep or idle mode.
In addition to the RCNR, the RTC incorporates a 32-bit, RTC Alarm register (RTAR). The RTAR
may be programmed with a value that is compared against the RCNR. One 32-KHz cycle after
each rising edge of the Hz clock, the counter is incremented and then compared to the RTAR. If the
values match, and the enable bit is set, then the RTC Status register (RTSR) alarm match bit
(RTSR[AL]) is set. This status bit is also routed to the interrupt controller and may be unmasked in
the interrupt controller to generate a processor interrupt. Another available interruptible status bit
that can be set whenever the Hz clock transitions is the RTSR. By writing a one to the AL or HZ bit
in the RTSR, the status bit is cleared.
The Hz clock is generated by dividing one of two selectable clock sources, both approximately
32.768 KHz in frequency. The first source is the output of the 3.6864-MHz crystal oscillator
further divided by 112 to approximately 32.914 KHz. The other source is the optional 32.768-KHz-
crystal-oscillator output itself. Your system may be built with both the 32.768-KHz-crystal
oscillator and the 3.6864-MHz-crystal oscillator. Alternately, your system may only use the
3.6864-MHz crystal oscillator, if the additional power consumption during sleep mode is
acceptable.
The divider logic for generating the Hz clock is programmable. This lets you trim the counter to
adjust for inherent inaccuracies in the crystal’s frequency and the inaccuracy caused by the division
of the 3.6864-MHz oscillator which yields only an approximate 32 KHz. The trimming mechanism
lets you adjust the RTC to an accuracy of +/- 5 seconds per month. The trimming procedure is
described in a later paragraph.
Note: Without trimming, a typical 50ppm oscillator only provides an accuracy of +/- 5 seconds per day.
All registers in the RTC, with the exception RTTR, are reset by hardware reset and the watchdog
reset. The trim register, RTTR is reset only by hardware reset.
4.3.2 Real-Time Clock Register Definitions
The following sections provide register descriptions for the RTC.