Intel PXA26X - Manual (Page 247)

Intel® PXA26x Processor Family Developer’s Manual 6-57
Memory Controller
Figure 6-20. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)
In Figure 6-20 some of the parameters are defined as follows:
• tAS = Address setup to nCS = 1 MEMCLK
• tCES = nCS setup to nWE = 2 MEMCLKs
• tASW = Address setup time to nWE asserted = 3 MEMCLKs
• tDSWH = Write data, DQM setup to nWE deasserted = (RDF+2) MEMCLKs
• tDH = Data, DQM hold after nWE deasserted = 1 MEMCLKs
• tCEH = nCS held asserted after nWE deasserted = 1 MEMCLK
• tAH = Address hold after nWE deasserted = 1 MEMCLKs
6.9 16-Bit PC Card/Compact Flash Interface
The following sections provide information on the card interface based on the PC Card Standard –
Volume 2 – Electrical Specification, Release 2.1, and CF+ and CompactFlash Specification
Revision 1.4. Only 8- and 16-bit data transfers are supported.
A0 A1
byte addr byte addr
CMD DATA
mask mask
tDH
tDSWH
RDF+1 RD RDF+1
tAH
tCEH
RD
tCES
tASW
tAS
RRR*2+1 RRR*2+1
MEMCLK
nCS[0]
MA[25:2]
MA[1:0]
nWE
nOE
RDnWR
MD[31:0]
DQM[3:0]
nADV(nSDCAS)