Intel PXA26X - Manual (Page 299)

Intel® PXA26x Processor Family Developer’s Manual 7-31
Liquid Crystal Display Controller
7.6.3.1 Beginning-of-Frame Line Clock Wait Count (BFW)
In active mode (LCCR0[PAS]=1), the 8-bit beginning-of-frame line clock wait count (BFW) field
specifies the number of line clocks to insert at the beginning of each frame. The BFW count starts
when the VSYNC signal for the previous frame is negated. BFW contains the number of line clock
periods to insert before starting pixel output in the next frame. BFW generates a wait period
ranging from 0 to 255 extra L_LCLK cycles (BFW=0x00 disables the wait count). L_LCLK does
toggle during the generation of the BFW line clock wait periods.
In passive mode, set BFW to zero so that no beginning-of-frame wait states are generated. Use
VSW exclusively in passive mode to insert line clock wait states. This lets the LCD controller’s
DMAC fill the palette and insert additional pixels before the start of the next frame.
7.6.3.2 End-of-Frame Line Clock Wait Count (EFW)
In active mode (LCCR0[PAS]=1), the 8-bit end-of-frame (EOF) line clock wait count (EFW) field
specifies the number of line clocks to insert at the end of each frame. Once a complete frame of
pixels is transmitted to the LCD display, EFW contains the number of line clock periods to wait.
Table 7-5. LCD Controller Control Register 2
Physical Address
0x4400_0008
LCD Controller Control Register 2 LCD Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFW EFW VSW LPP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:24 BFW
BEGINNING-OF-FRAME LINE CLOCK WAIT COUNT ( Section 7.6.3.1 ):
In active mode (LCCR0[PAS]=1), this value (0–255) specifies the number of line clock
periods to add to the beginning of a frame before the first set of pixels is sent to the display.
The line clock does toggle during the insertion of the extra line clock periods.
BFW must be cleared to zero (disabled) in passive mode.
23:16 EFW
END-OF-FRAME LINE CLOCK WAIT COUNT ( Section 7.6.3.2 ):
In active mode (LCCR0[PAS=1), this value (0–255) specifies the number of line clock
periods to add to the end of each frame. The line clock does toggle during the insertion of
the extra line clock periods.
EFW must be cleared to zero (disabled) in passive mode.
15:10 VSW
VERTICAL SYNC PULSE WIDTH ( Section 7.6.3.3 ):
In active mode (LCCR0[PAS]=1), this value (0–63) specifies the number of line clock
periods to pulse the L_FCLK pin at the end of each frame after the end-of-frame wait
(EFW) period elapses. Frame clock used as VSYNC signal in active mode. The line clock
does toggle during VSYNC. VSYNC width = (VSW+1)
In passive mode (LCCR0[PAS]=0), this value (0–63) specifies the number of extra line
clock periods to insert after the end-of-frame. The time for which L_FCLK is asserted is not
affected by VSW in passive mode. The line clock does toggle during the insertion of the
extra line clock periods. VSYNC width = (VSW+1).
9:0 LPP
LINES PER PANEL ( Section 7.6.3.4 ):
Specifies the number of lines per panel. For single-panel mode, this represents the total
number of lines on the LCD display. For dual-panel mode, it is half the number of lines on
the whole LCD display. Lines per panel = (LPP+1).