Intel PXA26X - Manual (Page 402)

11-8 Intel® PXA26x Processor Family Developer’s Manual
Fast Infrared Communication Port
The core must also read bytes from the FIFO until ICSR0[EIF] is cleared if there are errors in FIFO
entries below the DMA trigger level. When the entries below the DMA trigger level no longer
contain status flags, DMA requests are enabled.
11.3 Fast Infrared Communications Port Register
Descriptions
The FICP has six registers: three control registers, one data register, and two status registers. The
FICP registers are 32 bits wide, but only the lower 8 bits have valid data. The FICP does not
support byte or half-word operations. CPU reads and writes to the FICP registers must be word
wide.
The control registers determine: IrDA transmission rate, address match value, how transmit FIFO
underruns are handled, normal or active low transmit and receive data, whether transmit and
receive operations are enabled, the FIFO interrupt service requests, receive address matching, and
loopback mode.
The data register addresses the top of the transmit FIFO and the bottom of the receive FIFO. Reads
to the data register access the receive FIFO. Writes to the data register access the transmit FIFO.
The status registers contain: CRC, overrun, underrun, framing, and receiver abort errors; the
transmit FIFO service request; the receive FIFO service request; and end-of-frame conditions.
Each of these hardware-detected events signals an interrupt request to the interrupt controller. The
status registers also contain flags for transmitter busy, receiver synchronized, receive FIFO not
empty, and transmit FIFO not full (no interrupt generated).
11.3.1 FICP Control Register 0
The FICP control register 0 (ICCR0) contains eight valid bit fields that control various functions
for 4 Mbps IrDA transmission. The FICP must be disabled (RXE=TXE=0) when ICCR0[ITR] and
ICCR0[LBM] are changed. To allow various modes to be changed during active operation,
ICCR0[7:2] may be written when the FICP is enabled.