Figure 13-9. pcm transmit and receive operation, 10 mic-in control register (mccr), Table 13-16. mic-in control register – Intel PXA26X User Manual
Page 489
Intel® PXA26x Processor Family Developer’s Manual
13-27
AC97 Controller Unit
13.8.3.10
Mic-In Control Register (MCCR)
Figure 13-9. PCM Transmit and Receive Operation
Table 13-16. Mic-In Control Register
Physical Address
4050_0008
MCCR Register
AC97
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
FE
IE
R
eser
ved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:4
—
Reserved
3
FEIE
FIFO ERROR INTERRUPT ENABLE (FEIE):
This bit controls whether the occurrence of a receive FIFO error causes an interrupt or not.
0 – No interrupt will occur even if bit 4 in the MCSR is set
1 – An interrupt will occur if bit 4 in the MCSR is set.
2:0
—
Reserved
TxEntry0
TxEntry1
TxEntry2
TxEntry3
TxEntry15
31
Right
Left
16 15
0
RxEntry0
RxEntry1
RxEntry2
RxEntry3
RxEntry15
31
Right
Left
16 15
0
PCDR Register
31
0
Processor/DMA
TxFIFO
Written
Processor/DMA
RxFIFO
Read
PCM Transmit FIFO
PCM Receive FIFO
Write
Read
Transmit Data
Receive Data