Intel PXA26X - Manual (Page 12)

xii Intel® PXA26x Processor Family Developer’s Manual
Contents
15.5.5 MMC_CMDAT Register ....................................................................................15-25
15.5.6 MMC_RESTO Register ....................................................................................15-26
15.5.7 MMC_RDTO Register.......................................................................................15-27
15.5.8 MMC_BLKLEN Register ...................................................................................15-28
15.5.9 MMC_NOB Register .........................................................................................15-28
15.5.10 MMC_PRTBUF Register ..................................................................................15-28
15.5.11 MMC_I_MASK Register....................................................................................15-29
15.5.12 MMC_I_REG Register ......................................................................................15-30
15.5.13 MMC_CMD Register.........................................................................................15-31
15.5.14 MMC_ARGH Register ......................................................................................15-34
15.5.15 MMC_ARGL Register .......................................................................................15-34
15.5.16 MMC_RES FIFO (read only) ............................................................................15-35
15.5.17 MMC_RXFIFO FIFO (read only).......................................................................15-35
15.5.18 MMC_TXFIFO FIFO .........................................................................................15-35
16 Network/Audio Synchronous Serial Protocol Serial Ports ..........................................................16-1
16.1 Overview..........................................................................................................................16-1
16.2 Features...........................................................................................................................16-1
16.3 Signal Description............................................................................................................16-2
16.4 Operation .........................................................................................................................16-2
16.4.1 Processor and DMA FIFO Access......................................................................16-3
16.4.2 Trailing Bytes in the Receive FIFO .....................................................................16-3
16.4.3 Data Formats ......................................................................................................16-4
16.4.4 Hi-Z on SSPTXD...............................................................................................16-13
16.4.5 FIFO Operation.................................................................................................16-17
16.4.6 Baud-Rate Generation......................................................................................16-17
16.5 SSP Port Register Descriptions.....................................................................................16-18
16.5.1 SSP Control Register 0 (SSCR0) .....................................................................16-18
16.5.2 SSP Control Register 1 (SSCR1) .....................................................................16-21
16.5.3 SSP Programmable Serial Protocol Register (SSPSP) ....................................16-27
16.5.4 SSP Time Out Register (SSTO) .......................................................................16-28
16.5.5 SSP Interrupt Test Register (SSITR)................................................................16-29
16.5.6 SSP Status Register (SSSR)............................................................................16-30
16.5.7 SSP Data Register (SSDR) .............................................................................. 16-34
16.6 Register Summary .........................................................................................................16-34
17 Hardware UART .........................................................................................................................17-1
17.1 Overview..........................................................................................................................17-1
17.2 Features...........................................................................................................................17-2
17.3 Signal Descriptions ..........................................................................................................17-3
17.4 Operation .........................................................................................................................17-3
17.4.1 Reset ..................................................................................................................17-5
17.4.2 FIFO Operation...................................................................................................17-5
17.4.3 Autoflow Control .................................................................................................17-7
17.4.4 Auto-Baud-Rate Detection..................................................................................17-8
17.4.5 Slow Infrared Asynchronous Interface................................................................17-8
17.5 Hardware UART Register Descriptions .........................................................................17-10
17.5.1 Receive Buffer Register (RBR).........................................................................17-10
17.5.2 Transmit Holding Register (THR) .....................................................................17-11
17.5.3 Divisor Latch Registers (DLL and DLH)............................................................17-11