Intel PXA26X - Manual (Page 109)

Intel® PXA26x Processor Family Developer’s Manual 4-1
System Integration Unit
4
This chapter describes the System Integration Unit (SIU) for the Intel® PXA26x Processor Family.
The SIU controls several processor-wide system functions. The units contained in the SIU are:
• General-purpose I/O ports
• Interrupt controller
• Real-time clock
• Operating system timer
• Pulse width modulator
4.1 General-Purpose Input/Output
The PXA26x processor family enables and controls its 90 general purpose I/O (GPIO) pins through
the use of 27 registers which configure the pin direction (input or output), pin function, pin state
(outputs only), pin level detection (inputs only), and selection of alternate functions. A portion of
the GPIOs can be used to bring the processor out of sleep mode. Take care when choosing which
GPIO pin is assigned as a GPIO function because many of the GPIO pins have alternate functions
and can be configured to support processor peripherals.
Configure all unused GPIOs as outputs to minimize power consumption.
4.1.1 GPIO Operation
The PXA26x processor family provides 90 GPIO pins for use in generating and capturing
application-specific input and output signals. Each pin can be programmed as either an input or
output. When programmed to be an input, a GPIO can also serve as an interrupt source.
The first 86 GPIO pins, GPIO[85:0] are configured as inputs during the assertion of all resets, and
remain as inputs until they are configured otherwise.
Warning: GPIOs [89:86], behave differently. They have different default values on reset. On reset, these four
GPIOs are outputs. They default to their dedicated functionality and value on reset and sleep exit.
To use these as GPIOs, they must be set to their alternate function 1 (ALT_FN_1). In order to
preserve their output direction if the GPDR is written, the direction bits for these four GPIOs are
inverted: set is input, clear is output. Any external device using these GPIOs must be able to
function under these initial conditions.
Use the GPIO Pin Direction Register (GPDR) to set whether the GPIO pins are outputs or inputs.
When programmed as an output, the pin can be set high by writing to the GPIO Pin Output Set
Register (GPSR) and cleared low by writing to the GPIO Pin Output Clear Register (GPCR). The
set and clear registers can be written regardless of whether the pin is configured as an input or an
output. If a pin is configured as an input, the programmed output state occurs when the pin is
reconfigured to be an output.