The divisor’s reset value is 0x0002 – Intel PXA26X User Manual
Page 596
17-12
Intel® PXA26x Processor Family Developer’s Manual
Hardware UART
Load these divisor latches during initialization to ensure that the baud rate generator operates
properly. If each divisor latch is loaded with a 0, the 16X clock stops. The divisor latches are
accessed with a word write.
The baud rate of the data shifted in to or out of a UART is given by the formula:
For example, if the divisor is 24, the baud rate is 38400 bps.
The divisor’s reset value is 0x0002.
describe the DLL and DLH registers.
BaudRate
14.7456 MHz
16xDivisor
(
)
----------------------------------
=
Table 17-4.
Divisor Latch Register Low (DLL) Bit Definitions
Physical Address
0x4160_0000 (DLAB=1)
Divisor Latch Register Low(DLL)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
DLL
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
1
0
Bits
Access
Name
Description
31:8
N/A
—
Reserved – Read as unknown and must be written as zero.
7:0
R/W
DLL
Low byte compare value to generate baud rate
Table 17-5.
Divisor Latch Register High (DLH) Bit Definitions
Physical Address
0x4160_0004 (DLAB=1)
Divisor Latch Register High (DLH)
PXA26x processor family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
DLH
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
Bits
Access
Name
Description
31:8
N/A
—
Reserved – Read as unknown and must be written as zero.
7:0
R/W
DLH
High byte compare value to generate baud rate