4 operating system timer count register (oscr), Table 4-47. oscr bit definitions, 5 operating system timer status register (ossr) – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
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System Integration Unit
4.4.2.4
Operating System Timer Count Register (OSCR)
The OS Timer Count register is a 32-bit counter that increments on rising edges of the 3.6864-MHz
clock. This counter can be read or written at any time. It is recommended that the system write-
protect this register through the MMU protection mechanisms.
After the OSCR is written, there is a delay before the register is actually updated. Software must
make sure the register has changed to the new value before relying on the contents of the register.
shows the bitmap of the OS Timer Count register.
4.4.2.5
Operating System Timer Status Register (OSSR)
This status register contains status bits that indicate a match has occurred between any of the four
match registers and the OSCR. These bits are set when the match event occurs (following the rising
edge of the 3.6864-MHz clock) and the corresponding interrupt enable bit is set in the OIER
register. The OSSR bits are cleared by writing a one to the proper bit position. Writing zeros to this
register has no effect. Write all reserved bits as zeros and ignore all reads.
shows the bitmap of the OS Timer Status register.
Table 4-47. OSCR Bit Definitions
Physical Address
0x40A0_0010
OS Timer Count Register (OSCR)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OSCV
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:0>
OSCV
OS TIMER COUNTER VALUE:
The current value of the OS timer counter.