Intel PXA26X - Manual (Page 569)

Intel® PXA26x Processor Family Developer’s Manual 16-21
Network/Audio Synchronous Serial Protocol Serial Ports
16.5.2 SSP Control Register 1 (SSCR1)
SSCR1, shown in Table 16-4 , contains bit fields that control various SSP port functions. Before
enabling the port (using SSCR0[SSE]), the desired values for this register must be set.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 16-4. SSCR1 Bit Definitions (Sheet 1 of 6)
Physical Address
Base+0x04
SSCR1
PXA26x processor family Network/Audio
SSP Serial Ports
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTE
LP
TT
E
EB
CE
I
SC
FR
R
e
ser
ved
SC
LKD
IR
SFR
M
DIR
RW
OT
R
e
ser
ved
TSR
E
RS
RE
TIN
T
E
R
e
ser
ved
ST
RF
EFW
R
RFT TFT
MW
D
S
SP
H
SP
O
LB
M
TIE RI
E
Reset 0 0 0 0 ? ? 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Access Name Description
31 R/W TTELP
TRANSMIT HI-Z LATER PHASE:
This bit modifies the behavior of TTE. It causes SSPTXD to become Hi-
Z 1/2 phase (or one clock edge) later than normal.
This only occurs with the TI SSP format, and the PSP format if the SSP
is a slave to frame.
For TI SSP format, this means the SSPTXD is Hi-Z after the rising edge
after the LSB (The LSB is present a full clock).
For PSP format if the SSP is a slave to frame, this means the SSPTXD
is Hi-Z two clock edges after the LSB (the LSB is present a full clock).
If SSPSCLK is an input, the device driving SSPSCLK must provide
another clock edge.
0 – SSPTXD Hi-Z timing is as described below for TTE.
1 – SSPTXD Hi-Z timing is extended by 1/2 phase. Only valid for TI
SSP, and PSP if the SSP is a slave to frame.
30 R/W TTE
TRANSMIT HI-Z ENABLE:
This bit controls whether or not SSPTXD is driven or Hi-Z when the SSP
is idle.
For Microwire* SSPTXD is driven at the same clock edge that the MSB
is driven, and SSPTXD is Hi-Z after the next rising edge of SSPSCLK
for the LSB (1 clock edge after the clock edge that starts the LSB).
For SPI, SSPTXD is Hi-Z whenever SSPFRM is deasserted.
For TI SSP format, SSPTXD is driven with the MSB at the first rising
edge of SSPSCLK after SSPSFRM is asserted and is Hi-Z after the
falling edge of SSPSCLK for the LSB (1 clock edge after the clock edge
that starts the LSB).
For PSP format, if the SSP is a slave to frame SSPTXD is Hi-Z on the
same clock edge that starts the LSB. For PSP format if the SSP is a
master to frame, SSPTXD is Hi-Z on the clock edge after the clock edge
for the LSB. This occurs even if the SSP is a master of clock and this
clock edge does not appear on SSPSCLK.
0 – SSPTXD line is driven when SSP is idle
1 – SSPTXD line is Hi-Z when SSP is idle