10 power mode summary – Intel PXA26X User Manual
Page 86
3-20
Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
— The power manager wake-up source registers (PWER, PRER, and PFER) are loaded with
0x0000 0003, their wake-up default state. This limits the potential wake-up sources to a
rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious
events from causing an unwanted wake-up while the battery is low or the power supply is
at risk. The fault state is also the default state after a hardware reset.
2. The PLL clock generators are disabled.
3. If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864 MHz
oscillator is disabled. If the oscillator is disabled, sleep mode consumes less power. If it is
enabled, sleep mode exits more quickly.
4. An internal reset is generated to the core and most peripheral modules. This reset asserts the
nRESET_OUT pin.
5. The PWR_EN pin is deasserted. If PMFWR[FWAKE] is cleared, the system must respond by
grounding the VCC and PLL_VCC power supplies to minimize power consumption.
3.4.10
Power Mode Summary
Table 3-4
shows the actions that occur when a power mode is entered.
Table 3-5
shows the actions
that occur when a power mode is exited. In the tables, an empty cell means that the power mode
skips that step.
Table 3-6
shows the expected behavior for power supplies in each power mode.
Table 3-4. Power Mode Entry Sequence Table
St
e
p
Description of Action
Tu
rb
o
R
u
n (fr
om T
u
rbo)
Idle
Fr
eq C
h
ang
e
Sl
e
e
p
Fault
1
Sle
e
p
1
Software writes a bit in CP14
x
x
x
x
x
2
The CPU waits until all instructions to be completed
x
x
x
x
x
3
Wake up sources are cleared and limited to GP[1:0]
x
4
The power manager places GPIOs in their sleep states
x
x
5
The memory controller finishes all outstanding transactions
x
x
x
6
The memory controller places SDRAMs in self-refresh
x
x
x
7
The PLL is disabled
x
x
x
8
If OPDE and OOK bits are set, disable 3.6864 MHz oscillator
x
x
9
Internal reset to most modules. nRESET_OUT asserted
x
x
10
PWR_EN is deasserted.
x
x
NOTE: 1. Fault sleep mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.