Intel PXA26X - Manual (Page 468)

13-6 Intel® PXA26x Processor Family Developer’s Manual
AC97 Controller Unit
Note: When the ACUNIT transmits mono audio sample streams, software must ensure that the left and
right sample stream time slots are filled with identical data.
13.4.1.1 Slot 0: Tag Phase
In slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) that flags the validity for the entire
audio frame. If the valid frame bit is a 1, the current audio frame contains at least one slot time of
valid data. The next 12 bit positions sampled by AC97 indicate which of the corresponding 12 time
slots contain valid data. Bits 0 and 1 of slot 0 are used as codec ID bits for I/O reads and writes to
the codec registers as described in the next section. The codec can control the output sample rate of
the controller using the SLOTREQ bits as described later (in the Input frame description). This
way, data streams of differing sample rates can be transmitted across AC-link at its fixed 48-KHz-
audio-frame rate.
Figure 13-5 on page 13-9 illustrates the time slot-based AC-link protocol.
Codec ready, sent by the codec on its data out stream in slot 0 bit 15, is not expected to change
during normal operation. The AC97 Specification revision 2.0 requires that a codec only change its
codec ready status in response to a power down (PR) state change issued by the controller. The
controller hardware by itself does not monitor the codec ready for sending or receiving data. The
controller stores codec ready in GSR[PCR] for a primary codec and GSR[SCR] for a secondary
codec purely for software to trigger a DMA or a programmed I/O operation. The controller only
samples codec ready valid once and then ignores it for subsequent frames. Codec ready is only
resampled after a PR state change.
13.4.1.2 Slot 1: Command Address Port
The command port controls features and monitors status for AC97 functions including, but not
limited to, mixer settings and power management (refer to AC97 Specification revision 2.0 for
more details).
The control-interface architecture supports up to sixty-four16-bit read/write registers, addressable
on even byte boundaries. Only accesses to even registers (0x00, 0x02, etc.) are valid. Accesses to
odd registers (0x01, 0x03, etc.) are not valid.
Audio output frame slot 1 communicates control register address and write/read command
information to the ACUNIT.
Two codecs can be connected to the single SDATA_OUT signal. To address the primary and
secondary codecs individually, follow these steps:
To access the primary codec:
1. Set the Valid Frame bit (slot 0, bit 15)
2. Set the valid bits for slots 1 and 2 (slot 0, bits 14 and 13)
3. Write 0b00 to the codec ID field (slot 0, bits 1 and 0)
4. Specify the read/write direction of the access (slot 1, bit 19).
5. Specify the index to the codec register (slot 1, bits 18-12)
6. If the access is a write, write the data to the command data port (slot 2, bits 19-4)
To access the secondary codec:
1. Set the Valid Frame bit (slot 0, bit 15)
2. Clear the valid bits for slots 1 and 2 (slot 0, bits 14 and 13)