Intel PXA26X - Manual (Page 194)

6-4 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
The VLIO interface differs from SRAM in that it allows the data-ready input signal, RDY, to insert
a variable number of wait states. For all static memory types, each chip select can be individually
configured to a 16-bit or 32-bit-wide data bus. nOE is asserted on all reads, nPWE is asserted on
writes to VLIO devices, and nWE is asserted on writes to all other static devices, both synchronous
and asynchronous. For SRAM and VLIO, DQM[3:0] are byte selects for both reads and writes.
Normally reads from static memory devices assert all DQM signals and the lower address bits are
0, even if the actual data size read is less than a word. For the PXA26x processor family, a new
register has been added to force SA-1111 compatibility for devices such as PCI bridges, which
behave differently based on the transfer size.
When the processor comes out of reset, it starts fetches and executes instructions at address 0x0,
which corresponds to memory selected by nCS[0]. The internal flash is located at this address.
6.2.3 16-Bit PC Card / Compact Flash Interface
The processor card interface is based on The PC Card Standard - Volume 2 - Electrical
Specification, Release 2.1, and CF+ and CompactFlash Specification Revision 1.4. The 16-bit PC
Card/Compact Flash interface provides control signals to support any combination of 16-bit PC
Card/Compact Flash for two card sockets, using address line (MA[25:0]) and data lines
(MD[15:0]).
The PXA26x processor family adds support for 8 bit PC Card/ Compact Flash peripherals.
The processor 16-bit PC Card / Compact Flash controller provides the following signals.
• nPREG is muxed with MA[26] and selects register space (I/O or attribute) versus memory
space
• nPOE and nPWE allow memory and attribute reads and writes
• nPIOR, nPIOW, and nIOIS16 control I/O reads and writes
• nPWAIT allows extended access times
• nPCE2 and nPCE1 are byte select high and low for a 16-bit data bus
• PSKTSEL selects between two card sockets
6.3 Memory System Examples
This section provides examples of memory configurations that are possible with the processor.
Figure 6-2 shows a system that uses 1M x 16-bit x 4-bank SDRAM devices for a total of
48 Mbytes.