Intel PXA26X - Manual (Page 359)

Intel® PXA26x Processor Family Developer’s Manual 9-21
Inter-Integrated Circuit Bus Interface Unit
7. When an IDBR transmit empty interrupt occurs.
Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0)
8. Write a 1 to the ISR[ITE] bit to clear interrupt.
9. Repeat steps 5-8 one time.
10. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
11. Send repeated start as a master.
Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
12. When an IDBR transmit empty interrupt occurs.
Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (1)
13. Write a 1 to the ISR[ITE] bit to clear interrupt.
14. Initiate the read.
Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]
15. When an IDBR receive full interrupt occurs (unit is sending stop).
Read ISR: IDBR receive full (1), unit busy (x), R/nW bit (1), ACK/NAK bit (1)
16. Write a 1 to the ISR[IRF] bit to clear the interrupt.
17. Read IDBR data.
18. Clear ICR[STOP] and ICR[ACKNAK] bits
9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort
To read 2 bytes as a master and send a STOP using the abort:
1. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
2. Initiate the write.
Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
3. When an IDBR transmit empty interrupt occurs.
Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (1)
4. Write a 1 to the ISR[ITE] bit to clear interrupt.
5. Initiate the read
Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], clear ICR[ACKNAK], set ICR[TB]
6. When an IDBR receive full interrupt occurs.
Read ISR: IDBR receive full (1), unit busy (1), R/nW bit (1), ACK/NAK bit (0)
7. Write a 1 to the ISR[IRF] bit to clear the interrupt.
8. Read IDBR data.
9. Clear ICR[STOP] and ICR[ACKNAK] bits
10. Initiate the read.
Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]
ICR[STOP] is not set because STOP or repeated start will be decided on the byte read.
11. When an IDBR receive full interrupt occurs.
Read ISR: IDBR receive full (1), unit busy (1), R/nW bit (1), ACK/NAK bit (1)
12. Write a 1 to the ISR[IRF] bit to clear the interrupt.