Intel PXA26X User Manual
Page 87
Intel® PXA26x Processor Family Developer’s Manual
3-21
Clocks and Power Manager
.
Table 3-5. Power Mode Exit Sequence Table
St
e
p
Description of Action
Tu
rb
o
R
un (fr
om T
u
rb
o
)
Idle
Fr
eq C
h
a
n
ge
S
leep
Fault
1
S
leep
1
Wake up source or interrupt is received
x
x
x
2
Power to I/O pins restored
3
PWR_EN is asserted
x
x
4
External power ramp (if core supply was disabled in sleep)
x
x
5
Enable 3.6864 MHz oscillator if OPDE and OOK are set
x
x
6
Wait for 3.6864 MHz oscillator to stabilize if OPDE and OOK
are set
x
x
7
Enable PLL with new frequency
x
x
x
8
Wait for PLL stabilization
x
x
x
9
Wait for internal stabilization
x
x
10
Clear CP14 bit
x
x
11
Deassert nRESET_OUT
x
x
12
Restart CPU clocks, enable interrupts
x
x
x
x
x
x
NOTE: 1. Fault sleep mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.