4 pcm-out control register (pocr), Table 13-10. pcm-out control register, 5 pcm-in control register (picr) – Intel PXA26X User Manual
Page 486: Table 13-11. pcm-in control register (picr)
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Intel® PXA26x Processor Family Developer’s Manual
AC97 Controller Unit
13.8.3.4
PCM-Out Control Register (POCR)
13.8.3.5
PCM-In Control Register (PICR)
Table 13-10. PCM-Out Control Register
Physical Address
4050_0000
POCR Register
AC97
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
FE
IE
R
eser
ved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:4
—
Reserved
3
FEIE
FIFO ERROR INTERRUPT ENABLE (FEIE):
This bit controls whether the occurrence of a transmit FIFO error causes an interrupt or not.
0 – No interrupt will occur even if bit 4 in the POSR is set
1 – An interrupt will occur if bit 4 in the POSR is set.
2:0
—
Reserved
Table 13-11. PCM-In Control Register (PICR)
Physical Address
4050_0004
PICR Register
AC97
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
FEIE
R
e
ser
ve
d
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:4
—
Reserved
3
FEIE
FIFO ERROR INTERRUPT ENABLE (FEIE):
This bit controls whether the occurrence of a receive FIFO error causes an interrupt or not.
0 – No interrupt occurs even if bit 4 in the PISR is set
1 – An interrupt occurs if bit 4 in the PISR is set.
2:0
—
Reserved