Intel PXA26X - Manual (Page 326)

8-8 Intel® PXA26x Processor Family Developer’s Manual
Synchronous Serial Port Controller
“fullness” threshold that triggers an interrupt. Write to these registers before the SSP is
enabled after reset and only change when SSP is disabled.
• The SSPC Data Register (SSDR) is mapped as one 32-bit location that consists of two 16-bit
registers. One register is for write operations and transfers data to the transmit FIFO. The other
is for read operations and takes data from the receive FIFO. A write cycle, or burst write, loads
successive half-words into the transmit FIFO. The write data occupies the lower 2 bytes of the
32-bit word. A read cycle, or burst read, similarly transfers data from the receive FIFO. The
FIFOs are independent buffers that allow full duplex operation.
• The SSPC Status Register (SSSR) indicates the state of the FIFO buffers, whether the
programmable threshold has been passed, and whether a transmit or receive FIFO service
request is active. It also shows how many entries are occupied in the FIFO. Flag bits are set
when the SSPC is actively transmitting or receiving data, when the transmit FIFO is not full,
and when the receive FIFO is not empty. An error bit signals an overrun of the receive FIFO.
When the registers are programmed, reserved bits must be written as 0s and are read as undefined.
8.7.1 SSP Control Register 0 (SSCR0)
The SSPC Control Register 0 (SSCR0) contains five bit fields that control SSP data size, frame
format, external clock selection, clock divisor, and SSP enable.
Table 8-2 shows the bit locations
that correspond to the control bit fields in SSPC Control Register 0. The SSE bit is reset to a zero
state to ensure the SSP is disabled. The reset states for the other control bits are shown in the table,
but each reset state must be set to the desired value before the SSPC is enabled.