Intel PXA26X - Manual (Page 469)

Intel® PXA26x Processor Family Developer’s Manual 13-7
AC97 Controller Unit
3. Write a non-zero value (0b01, 0b10, 0b11) to the codec ID field (slot 0, bits 1 and 0)
4. Specify the read/write direction of the access (slot 1, bit 19).
5. Specify the index to the codec register (slot 1, bits 18-12)
6. If the access is a write, write the data to the command data port (slot 2, bits 19-4).
Only one I/O cycle can be pending across the AC-link at any time. The ACUNIT uses write and
read posting on I/O accesses across the link. For instance, a read of a codec register returns
immediately before the access crosses the link. To get the real data, software must monitor the
CAR[CAIP] bit. Software must verify that the bit is not set before an access attempt to ensure it is
the first access. A set CAR[CAIP] bit indicates that a codec access is pending. After the
CAR[CAIP] bit is cleared, the next codec access (read or write) can go through.
The exception to posted accesses is reads to the codec GPIO Pin Status register (address 0x54).
Codec GPIO Pin Status reads are returned immediately with the data from the last slot 12 receive.
A codec with a GPIO Pin Status register must constantly send the status of the register in slot 12.
For reads to the codec, the controller gives the codec a maximum of four frames to respond, after
which if no response is received, it returns a dummy read completion to the CPU (0xFFFF_FFFF),
and also sets the read completion status bit, GSR[RDCS].
13.4.1.3 Slot 2: Command Data Port
The command data port delivers 16-bit control register write data in the event that the current
command port operation is a write cycle (as indicated by slot 1, bit 19).
If the current command port operation is a read, the ACUNIT fills the entire slot time with zeroes.
13.4.1.4 Slot 3: PCM Playback Left Channel
Audio output frame slot 3 is the composite digital audio left playback stream. If a sample stream is
transferred with a resolution that is less than 20 bits, the ACUNIT fills all trailing non-valid bit
positions in the slot with zeroes.
13.4.1.5 Slot 4: PCM Playback Right Channel
Audio output frame slot 4 is the composite digital audio right playback stream. The ACUNIT fills
all trailing non-valid bit positions in the slot with zeroes.
Table 13-3. Slot 1 Bit Definitions
Bit Name Description
Bit(19) RW 1 = read, 0 = write
Bit(18:12) IDX Code register index
Bit(11:0) Reserved Stuff with 0s
Table 13-4. Slot 2 Bit Definitions
Bit Name Description
Bit(19:4) Control register write data Stuffed with 0s if current operation is a read
Bit(3:0) Reserved Stuffed with 0s