13 modem status register (msr) – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
Hardware UART
17.5.13
Modem Status Register (MSR)
The Modem Status Register (MSR) provides the current state of the control lines from the modem
or data set (or a peripheral device emulating a modem) to the processor. In addition to this current
state information, four bits of the MSR provide change information. MSR[3:0] are set when a
control input from the Modem changes state. They are cleared when the processor reads the MSR.
The MSR bit definitions are shown in
.
The status of the modem control lines do not affect the FIFOs. To use these lines for flow control,
IER[MIE] must be set. When an interrupt on one of the flow control pins occurs, the interrupt
service routine must disable the UART. The UART will continue transmission/reception of the
current character and then stop. The contents of the FIFOs are preserved. If the UART is re-
enabled, transmission continues from the point where it stopped.
2
N/A
—
Reserved – Read as unknown and must be written as zero.
1
R/W
RTS
REQUEST TO SEND:
Controls the status of the nRTS pin when AFE is clear. When AFE is set,
switches between full autoflow and half autoflow.
Autoflow mode disabled:
0 – nRTS pin is 1
1 – nRTS pin is 0
Autoflow mode enabled:
0 – Auto-RTS disabled. Auto flow works only with auto-CTS
1 – Auto-RTS enabled. Auto flow works with both auto-CTS and auto-RTS
In Loopback mode, controls status of CTS input signal.
0
N/A
—
Reserved – Read as unknown and must be written as zero.
Table 17-16.
MCR Bit Definitions (Sheet 2 of 2)
Physical Address
0x4160_0010
Modem Control Reg. (MCR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
AF
E
L
OOP
OU
T
2
R
eser
ved
RT
S
R
eser
ved
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
?
0
?
Bits
Access
Name
Description