Intel PXA26X - Manual (Page 347)

Intel® PXA26x Processor Family Developer’s Manual 9-9
Inter-Integrated Circuit Bus Interface Unit
In master-transmit mode, if the target slave-receiver device cannot generate the acknowledge pulse,
the SDA line remains high. The lack of an acknowledge NAK causes the I
2
C unit to set the
ISR[BED] bit and generate the associated interrupt when enabled. The I
2
C unit automatically
generates a STOP condition and aborts the transaction.
In master-receive mode, the I
2
C unit sends a negative acknowledge (NAK) to signal the slave-
transmitter to stop sending data. The ICR[ACKNAK] bit controls the ACK/NAK bit value that the
I
2
C bus drives. As required by the I
2
C bus protocol, the ISR[BED] bit is not set for a master-
receive mode NAK. The I
2
C unit automatically transmits the ACK pulse after it receives each byte
from the serial bus. Before the unit receives the last byte, software must set the ICR[ACKNAK] bit
to 1 (NAK). The NAK pulse is sent after the last byte to indicate that the last byte has been sent.
In slave mode, the I
2
C unit automatically acknowledges its own slave address, independent of the
value in the ICR[ACKNAK] bit. In slave-receive mode, an ACK response automatically follows a
data byte, independent of the value in the ICR[ACKNAK] bit. The I
2 C unit sends the ACK value
after it receives the eighth data bit in a byte.
In slave-transmit mode, the I 2 C unit receives a NAK from the master to indicate the last byte has
been transferred. The master then sends a STOP or repeated START. The ISR[UB] bit remains set
until a STOP or repeated START is received.
9.4.4 Arbitration
The I
2
C bus’ multi-master capabilities require I
2
C bus arbitration. Arbitration takes place when
two or more masters generate a START condition in the minimum hold time.
Arbitration can take a long time. If the address bit and the R/nW are the same, the arbitration
scheme considers the data. Because the I
2
C bus has a wired-AND nature, a transfer does not lose
data if multiple masters signal the same bus states. If the address and the R/nW bit or the data they
contain are different, the master signals a high state loses arbitration and shuts off its data drivers. If
the I
2
C unit loses arbitration, it shuts off the SDA or SCL drivers for the rest of the byte transfer,
sets the ISR[ALD] bit, and returns to slave-receive mode.
9.4.4.1 SCL Arbitration
Each master on the I
2
C bus generates its own clock on the SCL line for data transfers. As a result,
clocks with different frequencies may be connected to the SCL line. Because data is valid when a
clock is in the high period, bit-by-bit arbitration requires a defined clock synchronization
procedure.
Clock synchronization is through the wired-AND connection of the I
2
C interfaces to the SCL line.
When a master’s clock changes from high to low, the master holds down the SCL line for its
associated period (see
Figure 9-6 on page 9-10 ). A clock cannot switch from low to high if another
master has not completed its period. The master with the longest low period holds down the SCL
line. Masters with shorter periods are held in a high wait-state until the master with the longest
period completes. After the master with the longest period completes, the SCL line changes to the
high state and masters with the shorter periods continue the data cycle.