Intel PXA26X - Manual (Page 621)

Intel® PXA26x Processor Family Developer’s Manual 18-5
Internal Flash
;//--- Fill up registers with correct values -- 50 MHz
SDCLK0_50MHz
;//--- Check for 16/32 bit mode
ldr r3, =MSC0
ldr r3, [r3]
and r3, r3, #0x8
cmp r3, #0x8
beq SDCLK0_50MHz_16bit
;//--- Configure for 50 MHz/32 bit operation
ldr r3, =SXCNFG
ldr r4, =0x00009708
ldr r5, =0x00600060
ldr r6, =0x00030003
ldr r7, =0x60f1
b aligned_address_32
SDCLK0_50MHz_16bit
ldr r3, =SXCNFG
ldr r4, =0x00004b84
ldr r5, =0x0060
ldr r6, =0x0003
ldr r7, =0x60f1
b aligned_address_16
;//--- Send out values to registers
ALIGN 0x20
aligned_address_16
strh r5, [r4] ;/* Have to do 16 bit writes to 16 bit wide flash */
strh r6, [r4] ;/* Entering synch mode places flash in read array mode */
str r7, [r3] ;/* Write SXCNFG value */
b %F1 ;/* Delay the prefetcher enough for SXCNFG to be written */
1
;//--- Check for second 128 Mbit flash by checking for vector table at 0x01000000,
check first 4 words
ldr r8, =0x01000000
ldr r0, =0x00000000
ldr r1, [r0], #4
ldr r9, [r8], #4
cmp r1, r9
bne second_flash_16
ldr r1, [r0], #4
ldr r9, [r8], #4
cmp r1, r9
bne second_flash_16
ldr r1, [r0], #4
ldr r9, [r8], #4
cmp r1, r9
bne second_flash_16
ldr r1, [r0]
ldr r9, [r8]
cmp r1, r9
beq EndSynchronousMode
second_flash_16
;//--- If vector table is not found, check for flash ID
ldr r8, =0x01000000
ldr r9, =0x0090;/* Read identifier first bus cycle */