Intel PXA26X - Manual (Page 171)

Intel® PXA26x Processor Family Developer’s Manual 5-13
Direct Memory Access Controller
1. The DMAC transfers the required number of bytes from the I/O device addressed by
DSADRx[31:0] to the DMAC write buffer.
2. The DMAC transfers the data to the memory controller via the internal bus. DCMD[WIDTH]
specifies the width of the internal peripheral to which the transfer is being made.
3. At the end of the transfer, DTADRx is increased by the smaller value of DCMDx[LENGTH]
and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same number.
For a flow-through DMA write to an internal peripheral, use these settings for the DMAC register
bits:
• DSADR[SRCADDR] = internal peripheral address
• DTADR[TRGADDR] = external memory address
• DCMD[INCTRGADDR] = 1
• DCMD[FLOWSRC] = 1
• DCMD[FLOWTRG] = 0
5.2.2 Quick Reference for Direct Memory Access Programming
Use Table 5-5 as a quick reference sheet for programming the DMA.
Table 5-5. DMA Quick Reference for Internal Peripherals (Sheet 1 of 2)
Unit Function FIFO Address
Width
(bytes)
DCMD.
Width
(binary)
Burst Size
(bytes)
Source
or
Target
DRCMR
I2S
receive 0x40400080 4 11 8, 16, 32 Source 0x4000 0108
transmit 0x40400080 4 11 8, 16, 32 Target 0x4000 010c
BTUART
receive 0x40200000 1 01 8, 16, 32 Source 0x4000 0110
transmit 0x40200000 1 01
8, 16, 32 or
trailing
Target 0x4000 0114
FFUART
receive 0x40100000 1 01 8, 16, 32 Source 0x4000 0118
transmit 0x40100000 1 01
8, 16, 32 or
trailing
Target 0x4000 011c
AC97
microphone 0x40500060 4 11 8, 16, 32 Source 0x4000 0120
modem
receive
0x40500140 4 11 8, 16, 32 Source 0x4000 0124
modem
transmit
0x40500140 4 11 8, 16, 32 Target 0x4000 0128
audio receive 0x40500040 4 11 8, 16, 32 Source 0x4000 012c
audio transmit 0x40500040 4 11 8, 16, 32 Target 0x4000 0130
SSP
receive 0x41000010 2 10 8, 16 Source 0x4000 0134
transmit 0x41000010 2 10 8, 16 Target 0x4000 0138
FICP
receive 0x4080000C 1 01 8, 16, 32 Source 0x4000 0144
transmit 0x4080000C 1 01
8, 16, 32 or
trailing
Target 0x4000 0148