Intel PXA26X User Manual
Page 292
7-24
Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
When PAS=1, active mode is selected. 1- and 2-bit pixel modes are not supported in active mode.
For 4- and 8-bit pixel modes, pixel data is transferred via DMA from off-chip memory to the input
FIFO, unpacked, and used to select an entry from the palette, just as in passive mode. However, the
value read from the palette bypasses the LCD controller’s dither logic and is sent directly to the
output FIFO to be driven onto the LCD’s data pins. This 16-bit output to the pins represents 5 bits
of red, 6 bits of green, and 5 bits of blue data. For 16-bit pixel encoding mode, two 16-bit values
are packed into each word in the frame buffer. Each 16-bit value is transferred via DMA from off-
chip memory to the input FIFO. Unlike 4 and 8 bit per pixel modes, the 16-bit value bypasses both
the palette and the dither logic and is placed directly in the output FIFO to be sent to the LCD’s
data pins. Using the 16-bit pixel encoding mode allows a total of 64,000 colors to be generated.
The 16-bit output from either the palette or frame buffer to the pins can be organized in any fashion
necessary to correctly interface with the LCD panel. Typically, the output is configured into one of
three user-specified RGB color formats:
•
6 bits of red, 5 bits of green, and 5 bits of blue data
•
5 bits of red, 6 bits of green, and 5 bits of blue data
•
5 bits of red, 5 bits of green, and 6 bits of blue data
The RGB format 5:6:5 is normally used, since the human eye can distinguish more shades of green
than of red or blue.
The LCD pin timing changes when active mode is selected. Timing of each pin is described in
subsequent bit-field sections for both passive and active modes.
The LCD controller can be configured in active-color-display mode and used with an external
DAC and optionally an external palette to drive a video monitor. Only monitors that implement the
RGB data format can be used. The LCD controller does not support the NTSC standard. However,
the 2X pixel clock mode allows the LCD controller to easily interface with an NTSC encoder, such
as the Analog Devices 7171 encoder.
shows which bits are sent to the individual LCD data pins for both a
frame buffer entry (for 16-bit per pixel mode) and a selected palette entry (for 1, 2, 4 and 8 bit per
pixel mode). The pixel bits corresponding to L_DD pins when using an RGB format of 5:6:5 are
also shown. In active mode, L_DD pins [15:8] are also used. The user must configure the proper
GPIO pins for LCD operation to enable LCD controller operation. See
for GPIO configuration information.
The processor LCD controller may be used with active panels having more than 16 data pins, but
the panel will be limited to a total of 64,000 colors. There are three options:
•
To maintain the panel’s full range of colors and increase the granularity of the spectrum,
connect the LCD controller’s 16 data pins to the panel’s most significant R, G, and B pixel
data input pins and tie the panel’s least significant R, G, and B data pins either high or low.
•
To maintain the granularity of the spectrum and limit the overall range of colors possible,
connect the LCD controller’s 16-data pins to the panel’s least significant R, G, and B pixel
data input pins and tie the panel’s most significant data pins either high or low.
•
Sometimes, better results can be obtained by replicating the upper bits on the lower bits.