Intel PXA26X - Manual (Page 431)

Intel® PXA26x Processor Family Developer’s Manual 12-21
Universal Serial Bus Device Controller
b. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software enables
future reset interrupts by clearing the UDCCR[REM] bit.
3. Return from interrupt.
4. The host either asserts a USB reset or negates a USB reset.
5. The UDC generates a reset interrupt.
6. Software determines that the UDCCR[RSTIR] bit is set and clears the interrupt by writing a 1
to the UDCCR[RSTIR] bit. Software then examines the UDCCR[UDA] bit to determine the
type of reset that took place:
a. If UDCCR[UDA] is a 0, a reset assertion took place. Software returns from the interrupt
and waits for the reset negation interrupt.
b. If UDDCR[UDA] is a 1, a reset negation took place. Software sets any initialization that
is necessary.
7. Return from interrupt.
12.5.11 Case 11: SUSPEND Interrupt
1. As software starts, it clears the UDCCR[SRM] bit to allow a USB suspend interrupt.
2. The host PC asserts a USB suspend by stopping activity on the UDC+ and UDC- signals.
3. The UDC generates a suspend interrupt.
4. Software determines that the UDCCR[SUSIR] bit is set.This indicates that a USB suspend has
occurred and software takes any necessary actions to turn off other peripherals, clean up
internal buffers, perform power management, and perform similar functions. Software must
not disable the UDC and must not allow the processor to go into sleep mode while the USB
cable is attached.
12.5.12 Case 12: RESUME Interrupt
1. As software starts, it clears the UDCCR[SRM] bit to allow a USB resume.
2. The host PC asserts a USB resume by resuming activity after a suspend state on the UDC+ and
UDC- signals.
3. The UDC generates a resume interrupt.
4. Software determines that the UDCCR[RESIR] bit is set. This indicates that a USB resume has
occurred and the OS may take any necessary actions to turn on other peripherals, initialize
internal buffers, perform power management, and perform similar functions.
12.6 UDC Register Descriptions
All configuration, request/service, and status reporting is controlled by the USB host controller and
is communicated to the UDC via the USB. The UDC has registers that control the interface
between the UDC and the software. A control register enables the UDC and masks the interrupt
sources in the UDC. A status register indicates the state of the interrupt sources. Each of the sixteen
endpoints (control, OUT, and IN) have a control or status register. Endpoint 0 (control) has an