Intel PXA26X - Manual (Page 477)

Intel® PXA26x Processor Family Developer’s Manual 13-15
AC97 Controller Unit
Note: After it is enabled, the ACUNIT requests the DMA immediately to fill the transmit FIFO.
Note: The ACUNIT registers do not store the status of the DMA requests or information regarding the
number of data samples in each FIFO. As a result, programmed I/O must not be used in place of
DMA requests for data transfers.
Only the DMA can access the FIFOs. Accesses are made through the data registers. The DMA
controller accesses FIFO data in 8-, 16-, or 32-byte blocks. The DMA request thresholds are not
programmable.The ACUNIT makes a transmit DMA request when the transmit FIFO has less than
32 bytes. The ACUNIT makes a receive DMA request when the receive FIFO has 32 bytes or
more. Regardless of burst size, the DMA descriptor length must be a multiple of 32 bytes to
prevent audio artifacts from being introduced on the interface.
The DMA controller responds to the following ACUNIT DMA requests:
• PCM FIFO transmit and receive DMA requests made when the PCM transmit and receive
FIFOs are half full.
• Modem FIFO transmit and receive DMA requests made when the modem transmit and receive
FIFOs are half full.
• Mic-in receive DMA requests made when the mic-in receive FIFO is half full.
13.6.1 Initialization
The AC97 codec and ACUNIT circuitry reset on power up. After power up, the nACRESET signal
remains asserted until the audio or modem driver sets the GCR[COLD_RST] bit. During operation,
clearing the GCR[COLD_RST] bit resets the ACUNIT and codec. To initialize the ACUNIT
follow theses steps:
1. Program the GPIO Direction register and GPIO Alternate Function Select register to assign
proper pin directions for the ACUNIT ports. Refer to Section 13.3, “Signal Description” for
details.
2. Set the GCR[COLD_RST] bit to deassert nACRESET. Until this is done, all other registers
remain in a reset state. Deasserting nACRESET has the following effects:
a. Frames filled with zeroes are transmitted because the transmit FIFO is still empty. This
situation does not cause an error condition.
b. The ACUNIT records zeroes until the codec sends in valid data.
c. DMA requests are enabled.
3. Enable the primary ready interrupt enable or the secondary ready interrupt enable by setting
the GCR[PRIRDY_IEN] or the GCR[SECRDY_IEN] bits, respectively.
4. Software enables DMA operation in response to primary and secondary ready interrupts.
5. The ACUNIT triggers transmit DMA requests. The DMA fills the transmit FIFO in response.
6. The ACUNIT continues to transmit zeroes until the transmit FIFO is half full. When it is half
full, valid FIFO data is sent across the AC-link.
Note: When nACRESET is deasserted, a read to the codec mixer register returns the type of hardware
that resides in the codec. If the codec is not present or if the AC97 is not supported, the ACUNIT