Intel PXA26X - Manual (Page 263)

Intel® PXA26x Processor Family Developer’s Manual 6-73
Memory Controller
6.11.2.2 Boot-Time Configurations
The boot time configurations are shown in Figure 6-31 – Figure 6-33 . A boot from a single 32-
Mbit SMROM with nWORD = 1 is not supported. For the PXA260, BOOT_SEL[2:0] must be set
appropriately for the boot ROM. For the PXA261 and PXA262, BOOT_SEL[2:0] must be 0b001.
For the PXA263, BOOT_SEL[2:0] must be 0b000.
Three Configuration registers are affected at reset – MSC0:RBW0, MDREFR:E0PIN/K0RUN, and
SXCNFG.
Figure 6-31. Asynchronous Boot Time Configurations and Register Defaults
BOOT_SEL[2:0] = 000
Asynchronous
32-bit
ROM
32
MSC0
SXCNFG
7FF0 7FF0
0004 0004
RBW0 = 0
BOOT_SEL[2:0] = 001
Asynchronous
16-bit
ROM
16
MSC0
SXCNFG
7FF0 7FF8
0004 0004
RBW0 = 1
MDREFR 03CA 4FFF
E0PIN = 0, K0RUN = 0
MDREFR 03CA 4FFF
E0PIN = 0, K0RUN = 0
BOOT_SEL[2:0] = 000
BOOT_SEL[2:0] = 001
SXMRS
SXMRS
0000 0000
0000 0000