Intel PXA26X - Manual (Page 74)

3-8 Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
3.4.2.2 Behavior During Watchdog Reset
During watchdog reset, all units except the real time clock and parts of the clocks and power
manager maintain their defined reset conditions. All pins except the oscillator pins assume their
reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. All dynamic RAM
contents are lost during watchdog reset because the memory controller receives a full reset.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA26x Processor Family” on page 2-9 for
the pin states during watchdog and other resets.
3.4.2.3 Completing Watchdog Reset
Watchdog reset immediately reverts to a hardware reset when the nRESET pin is asserted.
Otherwise, the completion sequence for watchdog reset is:
1. The watchdog reset source is deasserted after t
DHW_OUT
. Refer to the Intel® PXA26x
Processor Family Electrical, Mechanical, and Thermal Specification.
2. The 3.6864 MHz oscillator and internal phase locked loop clock generators wait for
stabilization. The 32.768-KHz oscillator’s configuration and status are not affected by
watchdog reset.
3. The nRESET_OUT pin is deasserted. Refer to the Intel® PXA26x Processor Family
Electrical, Mechanical, and Thermal Specification.
4. The normal boot-up sequence begins. All processor units except the RTTR in the real time
clock and parts of the clocks and power manager return to their predefined reset conditions.
Software must examine the RCSR to determine the cause for the reboot.
3.4.3 GPIO Reset
GPIO reset is invoked when GP[1] is properly configured as a reset source and is asserted low for
greater than four 3.6864 MHz clock cycles. In GPIO reset all the processor units except the real
time clock, parts of the clocks and power manager, and the memory controller return to their
predefined, known states.
3.4.3.1 Invoking GPIO Reset
To use the GPIO reset function, configure it through the GPIO controller. The GP[1] pin must be
configured as an input and set to its alternate GPIO reset function in the GPIO controller. The
GPIO reset alternate function is level-sensitive and not edge-triggered. To ensure no spurious resets
are generated when the alternate GPIO reset function is set, follow these steps:
1. GP[1] must be set up as an output with its data register set to a 1.
2. Externally drive the GP[1] pin to a high state.
3. Configure GP[1] as an input.
4. Configure GP[1] for its alternate (reset) function.
The previous mode of operation does not affect a GPIO reset. When GPIO reset is invoked,
nRESET_OUT is asserted. If GP[1] is asserted for less than four 3.6864 MHz clock cycles, the
processor may remain in its previous mode or enter GPIO reset.