12 modem control register (mcr) – Intel PXA26X User Manual
Page 610
17-26
Intel® PXA26x Processor Family Developer’s Manual
Hardware UART
17.5.12
Modem Control Register (MCR)
The Modem Control Register (MCR) uses the modem control pin nRTS to control the interface
with a modem or data set. The MCR also controls the Loopback mode. Loopback mode must be
enabled before the UART is enabled. The MCR bit definitions are shown in
2
R
PE
PARITY ERROR:
Indicates that the received data character does not have the correct even or
odd parity, as selected by the even parity select bit. PE is set upon
detection of a parity error and is cleared when the processor reads the LSR.
In FIFO mode, PE shows a parity error for the character at the front of the
FIFO, not the most recently received character.
0 – No Parity error
1 – Parity error has occurred
1
R
OE
OVERRUN ERROR:
In non-FIFO mode, indicates that data in the Receive Buffer Register was
not read by the processor before the next character was received. The new
character is lost. In FIFO mode, OE indicates that all 64 bytes of the FIFO
are full and the most recently received byte has been discarded. The OE
indicator is set upon detection of an overrun condition and cleared when the
processor reads the LSR.
0 – No data has been lost
1 – Received data has been lost
0
R
DR
DATA READY:
Set when a complete incoming character has been received and
transferred into the Receive Buffer Register or the FIFO. In non-FIFO
mode, DR is cleared when the receive buffer is read. In FIFO mode, DR is
cleared if the FIFO is empty (last character has been read from RBR) or the
FIFO is reset with FCR[RESETRF].
0 – No data has been received
1 – Data is available in RBR or the FIFO
Table 17-15.
LSR Bit Definitions (Sheet 3 of 3)
Physical Address
0x4160_0014
Line Status Reg. (LSR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
FIFO
E
TEM
T
TD
R
Q
BI
FE
PE
OE
DR
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
1
1
0
0
0
0
0
Bits
Access
Name
Description