Intel PXA26X - Manual (Page 309)

Intel® PXA26x Processor Family Developer’s Manual 7-41
Liquid Crystal Display Controller
Software must load the palette at least once after enabling the LCD. Otherwise, the palette entries
will not be initialized, and the frame data will not have a valid frame palette to reference.
The palette must not be loaded if the LCD is operating in 16-bit pixel mode.
Note: Never set the PAL bit in LDCMD1, since the palette is always loaded with Channel 0.
7.6.5.5.2 Start Of Frame Interrupt (SOFINT)
When SOFINT=1, the DMAC sets the start of frame bit (LCSR[SOF]) when starting a new frame.
The SOF bit is set after a new descriptor is loaded from memory and before the palette/frame data
is fetched.
In dual-panel mode, LCSR[SOF] is set only when both channels reach the start of frame and both
frame descriptors have SOFINT set. SOFINT must not be set for palette descriptors in dual-panel
mode, since only one channel is ever used to load the palette RAM.
7.6.5.5.3 End Of Frame Interrupt (EOFINT)
When EOFINT is set to one, the DMAC sets the end of frame bit (LCSR[EOF]) after fetching the
last word in the frame buffer.
In dual-panel mode, LCSR[EOF] is set only when both channels reach the end of frame and both
frame descriptors have EOFINT set. EOFINT must not be set for palette descriptors in dual-panel
mode, since only one channel is ever used to load the palette RAM.
7.6.5.5.4 Transfer Length (LEN)
The LEN bit field determines the number of bytes fetched by the DMAC. LEN=0 is not valid. If
PAL=1, LEN must be programmed with the size of the palette RAM. This corresponds to:
8 bytes for 1- and 2-bit pixels (only the top 2 entries are actually used for 1-bit pixels)
32 bytes for 4-bit pixels
512 bytes for 8-bit pixels.
Note: Use a separate descriptor to fetch the frame data.
The value of LEN for frame data is a function of the screen size and the pixel size and it must be
consistent with the values used for LCCR1[PPL], LCCR2[LPP], and LCCR3[BPP]. See
Section 7.4.2, “External-Frame Buffer” for instructions on calculating length. The LCD DMAC
decrements LEN as it fetches data, allowing the user to read the number of bytes remaining for the
current descriptor.
7.6.6 LCD DMA Frame Branch Registers (FBRx)
The two Frame Branch registers, one for each DMA channel, are shown in Table 7-11 . They
contain the branch to descriptor addresses, aligned on a 4-byte boundary.
When BRA is set to one, the Frame Descriptor Address Register is ignored. The next descriptor is
fetched from the address in FBRx[31:4], regardless of whether frame data or palette RAM data is
being processed. Setting BINT=1 forces the DMAC to set the Branch Status interrupt bit (BS) in
the LCD Controller Status Register after fetching the branched-to descriptor. BRA is automatically
cleared by hardware when the branch is taken.